Blog
micro-nova.com made a rather unique FPGA development board. It packs a Xilinx Spartan-3A 200K and all its support circuitry onto a 64-pin DIP package. It is USB programmable, and also has an on-board 8-channel ADC, easy to interface to SRAM and 5-volt tolerant I/O pins, all for a very competitive price.
Features:
- Xilinx Spartan-3A FPGA – 200,000 gates
- 50MHz crystal oscillator
- 5-volt tolerant I/O pins
- 8 channel, 200 kSps, 10-bit ADC
- 4 Mbit asynchronous SRAM
- 2 Mbit configuration Flash
- Mini-USB and JTAG programmable
Mercury FPGA module in DIP format - [Link]
New multicore DSP devices from the French firm Kalray aim to surpass FPGAs in compute-intensive tasks, such as image and signal processing, 3D augmented reality and industrial automation. The company recently demonstrated the MPPA-256, the first member of their MPPA Manycore family of processors, at CEATEC Japan.
The MPPA-256 is organized as an array of 16 clusters of 16 cores interconnected by a high-bandwidth on-chip network. The proprietary cores are based on a VLIW low-power design and integrate a 32-/64-bit floating point unit. The cores of each cluster share memory, network interfaces, a debug support unit and control logic.
The demo applications at CEATEC include H.264 video encoding of a live 1080p stream from a source with a Serial Digital Interface (SDI), using a parallel implementation of the x264 open-source encoder, an industrial automation demo featuring a set of 17 Programmable Logic Controllers (PLC) running independently and concurrently on the same chip, and a passive sonar application demonstrating the capabilities of the MPPA-256 for complex signal processing tasks. [via]
Massively Parallel DSPs Challenge FPGAs - [Link]
The ATF697FF is the newest member of Atmel’s SPARC V8 processor family and the industry’s first radiation-hardened (RAD Hard) high-performance aerospace microprocessor that can be reconfigured on-the-fly. The ability to reconfigure on-the-fly allows making on-going design modifications to satellites, including specification updates, in-flight adjustments during trial flights and post-launch alterations.
The new device is a reconfigurable processor that combines an AT697F processor and an ATF280F SRAM-based FPGA unit in a single multichip module. It can run at speeds up to 100MHz and it is low-power, down to 0.7W. Designed and developed by the Atmel Aerospace Business Unit in Rousset, France, adds the flexibility of a reprogrammable FPGA to the reliability of a powerful core processor running application software. It is targeted at systems that require reconfiguration of peripherals and interfaces, making it easy to comply and stay up-to-date with evolving standards that are used on many space missions, such as SpaceWire, CAN or IEEE1553. The flexibility of the ATF697FF processor is also beneficial for late design modifications performed on Earth, for in-flight adjustments on satellites and for space trial operations. [via]
Reconfigurable Processor for Space Applications - [Link]
This project shows you how an accelerometer works, how it can be used to detect tilt and also how we can display that tilt -value- visually on a large array of LEDs on my DE0-Nano FPGA breakout board. chris @ pyroelectro.com writes:
After building a 40 pin breakout board for my DE0-Nano I wanted to test it out with something fun but not overly complex. The DE0-Nano has an on-board accelerometer which can sense changes in acceleration and tilt, so I figured why not try to do something cool with it.
This article will show you how an accelerometer works, how it can be used to detect tilt and also how we can display that tilt ‘value’ visually on a large array of LEDs on my DE0-Nano breakout board. This way whenever we need to see if something is level, we can use this simple but fun tool to know, although don’t count on multiple decimal precision here!
DE0-Nano FPGA Tilt Sensing - [Link]
Magnusk designed the Pipistello Spartan 6 development board with the same IO headers as the Papilio One. It features 64MB of RAM running at 200Mhz, the FDTI FT2232H High Speed USB IC, HDMI output, and a micro-SD card holder. [via]
So the only option left was to make my own board – basically merging the FPGA and LPDDR from the LX9-Microboard with the form-factor, wing interface and tool-set from Papilio, then adding all the needed interfaces on-board (and then some more to make it more interesting).
Pipistrello: Spartan 6 development board with 64MB of RAM, High Speed USB, and HDMI - [Link]
This article goes through the process of building your own i/o expander breakout board for the DE0-Nano Altera FPGA demo board. The PCB built easily connects to a breadboard where you have access to each individual FPGA I/O pin.
DIY DE0-Nano Breakout Board - [Link]
This project explains how to use an FPGA or CPLD to take input from one device (an ADC) and then output appropriate signals to a motor controller IC, that provides precise control over the DC motor’s speed and direction.
Since we now know how to create PWM output with a CPLD or FPGA and we also know how to understand dynamic analog input using an A-to-D converter, we can actually combine these two functions together and create an FPGA DC motor controller!
Even though I have written many, other, motor control articles, none of them used a CPLD or FPGA as the main controller. This article will focus on explaining how to use a CPLD to take input from one device and then output appropriate signals to a motor controller IC, that will give us precise control over the DC motor’s speed and direction.
FPGA DC Motor Control - [Link]
This article shows you how to create a VHDL module in an FPGA or CPLD that can output a dynamic PWM signal to fade LEDs in and out, creating a cool visual effect. The hardware schematic, source code, parts list and theory are all included in the article.
CPLD LED Fading - [Link]
Solutions Cubed, LLC writes:
In a generic electronic system there are some inputs that are controlled by the end user. These inputs are read by electronics and acted upon by using outputs. The inputs can come from a myriad of sources: buttons, switches, sensors, relays, and communication devices, to name a few. In certain environments and situations, these input signals can pose a threat to the electronics reading them – especially if those electronics are designed without thought of protection. One such environment is the world of industrial electronics.
An important aspect of designs for this environment is interfacing sensitive electronics with inputs coming from the harsh conditions of a factory floor. Usually, inputs are read by some sort of intelligent processor such as a microcontroller, FPGA, or state machine. In cases like these, it is imperative to protect the processor from the inputs, while still providing a usable signal for the processor to read.
Protecting Inputs in Digital Electronics - [Link]
ZPUino is a system-on-chip 32bit microprocessor FPGA core, that functions with a modified Arduino IDE. All the files regarding the core are open-source and downloadable from their site, and so is the modified Arduino IDE. [via]
Yes, that is true.
ZPUino 1.0 is now available for you to use and enjoy. Expect some updates on next few days – release cycles are about to change, we’re switching to release early, release often. As always, direct any questions to zpuino @ alvie.com.
ZPUino v1.0 released - [Link]
