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17 Mar 2014


A XC6SLX9 based design with a soft CPU and USB device interface implemented in Verilog.

This features my AltOR32 OpenRISC compatible CPU running at 48MHz which hosts a cutdown USB 1.1 (Full Speed) device, SPI master and GPIO interfaces.

The nice thing about this implementation is the low chip count (only required components are the FPGA, LDOs, SPI Flash & USB PHY).

Also, as the USB 1.1 device is implemented in the FPGA rather than an external USB to serial bridge, I’m free to implement other USB class devices (such as Audio, MSD, etc).

Currently comes with USB CDC device stack (virtual COM port). RTL, SW & schematics provided.

FPGA Based ‘Bus Pirate’ clone - [Link]

1 Mar 2014

The ring counter is useful in hardware logic design such as Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA). The ring counter is also ideal in creating simple finite state machines.

The diagram is a circuit of a 4-bit twisted ring counter which can function in 4 different modes, namely: Serial-Input-Serial-Output (SISO), Serial-Input-Parallel-Output (SIPO), Parallel-Input-Serial-Output (PISO), and Parallel-Input-Parallel-Output, by applying Qo to the serial input, the resulting circuit will be a twisted ring or a Johnson Counter.  Twisted ring counters are shift registers where the output from the last flip-flop becomes the input of the first flip-flop; it will result in a closed loop circuit which recirculates the data bits around a continuous loop for every sequence state.

The circuit is composed of NAND gates, flip-flops, voltage sources, and clocking system. The NAND gates are incorporated in a Quad-2 input NAND Gate integrated circuit with part number 74ABT00D. The NAND gates receive the inputs from D0, D1, D2, and D3. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. The circuit also uses JK flip flops as the memory element. For this circuit, the dual JK flip-flop IC with part number 74HC109D is used. Two 74HC109D chips are used since the circuit needs four JK flip-flops and each IC has two JK flip-flops in it. The 74HC109 is a dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.  The set and reset are asynchronous active LOW inputs and operate independently of the clock input.  The supply voltages used to power the ICs are set at 5V for 74ABT00D IC and -1.5V for the 74ABT00D IC. The clocking system connected to the flip-flops provide synchronization pulses and timing for the circuit.


  • 74ABT00D Quad-2 input NAND Gate
  • 74HC109D Dual Positive-edge triggered JK flip-flops
  • Clocking system
  • +5V DC Voltage Source
  • -1.5V DC Voltage Source

4-bit Twisted Ring Counter using JK Flip Flops – [Link]

10 Jan 2014


DSLogic is an interesting open source 200MHz logic analyzer project on Kickstarter.

Most of electronic instruments are designed in professional fashion. They are dedicated, traditional, well functioned, and most importantly, expensive. They are usually only available and affordable to academic and industry. Individuals, however, are not lucky enough to get the best electronic instruments as they want. This is how we are inspired to make DSLogic. [...]

DSLogic consists of DSLogic-Core and extension modules. DSLogic-Core is a re-configurable circuit board based on FPGA technology with maximum 200MHz sampling rate and 64Mbit on-board memory. DSLogic-Core can work alone as a fully functional logic analyzer, along with various extension modules. DSLogic can also work as oscilloscope, data acquisition system, protocol analyzer and even RF analyzer.

DSLogic – Multifunction Instruments For Everyone - [Link]

26 Nov 2013

Terasic’s DE0-Nano houses the Altera Cyclone IV that features a low cost, low power FPGA ideal for high-volume and cost-sensitive applications. Boosting a miniature size of 49 x 75 mm and a weight of 40 g, the board was aimed for simple implementations targeting the Cyclone IV up to 22,320 LEs. The device utilizes small spacers as legs and even an acrylic cover on top of the board to provide better protection making this Development kit (Devkit) the option to choose for robust applications while giving of a sleek feel to users as they get to look through the device’s glass-like cover. The DE0-Nano definitely is one device to consider in making portable design projects where portable power is essential.

Running at around $80, users already get to enjoy a lot of other on board features. The DE0-Nano is equipped with a 3-axis digital accelerometer designed for better sensing applications. Other on board features follow in the form of 2 separate extension headers plus a third header that supports an ADC converter with 8-channels and 16 I/O Pins, 8 user LEDs, Push buttons and DIP switches. DE0-Nano also provides a three-power scheme option for designers through a USB mini-AB port, 2-pin external power header and two DC 5V pins.

Upon connection to the host PC, the FPGA Devkit automatically powers up and the LEDs start fading in and out. Once host PC has loaded up the DE0-Nano Control Panel, the LEDs stop fading indicating a full user access of the device. The DE0-Nano Control Panel is a GUI that allows users to automatically verify hardware components of the board. Users get to play around the LEDs and a GUI representation is also provided for the Push buttons and DIP switches. The control panel also allows users to work around with the memory and verify accelerometer coordinates and even provides an ADC tab that allows users to monitor the voltage levels in the different channels. The DE0-Nano Control Panel has a user-friendly interface that provides a fast response GUI that readily illustrates all changes made in the actual board. In general, the device is a great development board. It already has everything on board without having to pay for a lot of extras. Despite the DE0-Nano being an entry-level device, the well thought out and compact design definitely makes it a very complete and functional development board.

Terasic DE0 Nano – Product Overview - [Link]

22 Aug 2013


Lattice Semi has released their iCEstick eval board. This board has a high-performance, low-power iCE40HX1K FPGA on board and has a USB thumb drive form factor. IO connectors include 16 LVCMOS/LVTTL (3.3 V) digital I/O connections on 0.1” through-hole connections and a 2 x 6 position Digilent Pmod connector for other peripheral connections. The board’s FTDI 2232H USB device allows iCE device programming and UART interface to a PC. On board devices include a Vishay TFDU4101 IrDA transceiver and five user LEDs. The board also includes a Discera 12 Mhz MEMS oscillator, Micron 32 Mbit N25Q32 SPI flash and is powered directly from the USB connector. [via]

Lattice debuts iCEstick FPGA Evaluation Board at $24.99 - [Link]

20 Jul 2013

What is an FPGA, and how does it compare to a microcontroller? A basic introduction to what Field Programmable Gate Arrays are and how they work, and the advantages and disadvantages.

EEVblog #496 – What Is An FPGA? - [Link]

19 Jun 2013


Steven Keeping writes:

Non-isolated buck or step-down DC/DC converters are needed as point-of-load (POL) regulators to power devices such as microprocessors, ASICs, FPGAs, and other semiconductor loads on system boards in telecom, datacom, and industrial applications. Due to recent advances in process technologies, packaging, and magnetics, buck converter solutions have been developed that deliver a complete power supply in a package (PSiP). Incorporating a switching controller, power MOSFETs, capacitors and magnetics in a single compact package, these integrated buck converters are raising the bar in power density and efficiency while offering the performance needed to meet the stringent power supply requirements of new-generation systems.

Digital Voltage Regulator Control Using PMBus - [Link]

18 Nov 2012

micro-nova.com made a rather unique FPGA development board. It packs a Xilinx Spartan-3A 200K and all its support circuitry onto a 64-pin DIP package. It is USB programmable, and also has an on-board 8-channel ADC, easy to interface to SRAM and 5-volt tolerant I/O pins, all for a very competitive price.


  • Xilinx Spartan-3A FPGA – 200,000 gates
  • 50MHz crystal oscillator
  • 5-volt tolerant I/O pins
  • 8 channel, 200 kSps, 10-bit ADC
  • 4 Mbit asynchronous SRAM
  • 2 Mbit configuration Flash
  • Mini-USB and JTAG programmable

Mercury FPGA module in DIP format - [Link]

15 Oct 2012

New multicore DSP devices from the French firm Kalray aim to surpass FPGAs in compute-intensive tasks, such as image and signal processing, 3D augmented reality and industrial automation. The company recently demonstrated the MPPA-256, the first member of their MPPA Manycore family of processors, at CEATEC Japan.

The MPPA-256 is organized as an array of 16 clusters of 16 cores interconnected by a high-bandwidth on-chip network. The proprietary cores are based on a VLIW low-power design and integrate a 32-/64-bit floating point unit. The cores of each cluster share memory, network interfaces, a debug support unit and control logic.

The demo applications at CEATEC include H.264 video encoding of a live 1080p stream from a source with a Serial Digital Interface (SDI), using a parallel implementation of the x264 open-source encoder, an industrial automation demo featuring a set of 17 Programmable Logic Controllers (PLC) running independently and concurrently on the same chip, and a passive sonar application demonstrating the capabilities of the MPPA-256 for complex signal processing tasks. [via]

Massively Parallel DSPs Challenge FPGAs - [Link]

31 Aug 2012

The ATF697FF is the newest member of Atmel’s SPARC V8 processor family and the industry’s first radiation-hardened (RAD Hard) high-performance aerospace microprocessor that can be reconfigured on-the-fly. The ability to reconfigure on-the-fly allows making on-going design modifications to satellites, including specification updates, in-flight adjustments during trial flights and post-launch alterations.

The new device is a reconfigurable processor that combines an AT697F processor and an ATF280F SRAM-based FPGA unit in a single multichip module. It can run at speeds up to 100MHz and it is low-power, down to 0.7W. Designed and developed by the Atmel Aerospace Business Unit in Rousset, France, adds the flexibility of a reprogrammable FPGA to the reliability of a powerful core processor running application software. It is targeted at systems that require reconfiguration of peripherals and interfaces, making it easy to comply and stay up-to-date with evolving standards that are used on many space missions, such as SpaceWire, CAN or IEEE1553. The flexibility of the ATF697FF processor is also beneficial for late design modifications performed on Earth, for in-flight adjustments on satellites and for space trial operations. [via]

Reconfigurable Processor for Space Applications - [Link]





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