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13 Aug 2014

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by Joel Williams @ joelw.id.au:

I bought Avnet’s $49 Spartan 3A development board but it was discontinued not long afterward – right about the time when I decided I needed a few dozen more. I’ve since done some extensive research (thanks, Google!) to find a comparable thrifty thrill.

When choosing a development board, consider what you get with it and what you want to use it for. FPGAs are ideal for use with high speed peripherals, and in general it is much easier to buy a board that contains the part you want, rather than trying to add one on later (and inevitably giving up and upgrading to a more capable board).

Cheap FPGA Development Boards – What to look for - [Link]

5 Aug 2014

contest

PyroElectro.com proudly presents their new contest:

View the Pyro Propeller Clock POV Project to learn more about the concept Persistence of Vision (POV) – a phenomenon where an afterimage persists for roughly one twenty-fifth of a second on the retina after the stimulus that produced it is removed.

Build an original electronic device demonstrating POV and photograph in action in a darkened environment. You may use any electronic parts desired as long as the POV signals are driven by either an FPGA or CPLD.

Submit your entry to contests@pyroelectro.com with the subject line “PyroElectro POV Contest.” Your entry must contain two photos of the device – one of its components in a well-lit environment and one of it in action in a darkened environment – as well as a circuit diagram and the VHDL code to run the device.

Who Can Build The Best P-O-V Contest - [Link]

30 Jul 2014

NIsom

by elektor.com:

National Instruments has introduced an embedded System-on-module (SOM) development board with integrated Linux-based real-time operating system (RTOS).

Processing power in the 2” x 3” SOM comes from a Xilinx Zync-7020 all programmable SOC running a dual core ARM Cortex-A9 at 667 MHz. A built-in low power Artix-7 FPGA offers 160 single-ended I/Os and Its dedicated processor I/O include Gigabit Ethernet USB 2.0 host, USB 2.0 host/device, SDHC, RS232 and Tx/Rx. Power requirements of the SOM are typically 3 to 5 W.

Linux embedded SOM from NI - [Link]

5 Jul 2014

Lat

Michael Dunn @ edn.com writes:

Whether engineer, hobbyist, or maker, we’ve happily watched as chipmakers and third parties alike have come to their senses in recent years and cooked up a smorgasbord (smorgasboard?) of low-cost microcontroller devboards – in some cases, very low cost, like TI’s $4.30 MSP430 board. More recently, we’ve seen ARM Cortex kits for $10-$50, the flowering of the whole Arduino ecosystem, and of course, the Raspberry Pi, starting at $25. It’s microcontroller heaven.

Those of us wanting a cheap “in” to the FPGA world have been less lucky. But the times, they are a changin’. Many FPGA devkits, from both chipmakers and third parties, have broken – or downright shattered – the $100 barrier, opening the door to low-cost FPGA prototyping, education, hobby projects, and so on.

Follow me as I explore this brave new world of affordable FPGA learning and design. I’ve acquired a representative selection of bargain-priced boards, and will be reviewing each, not just on paper, but by actually creating projects with it.

FPGA boards under $100: Introduction - [Link]


27 Jun 2014

pyroelectro.com just started an online course, An Introduction To FPGA And CPLD, through uReddit.com.

This course is meant to create a pathway into learning about FPGA and CPLD electronics, for people who are scared of the code, tools and general trickery that usually comes with it. A hands-on approach is taken in this course through a combination of lecture and experimentation to teach you about the different features of both the development tools and languages used in the world of FPGA. Additionally, visuals are used throughout lectures like step-by-step schematic building and line-by-line code explanations so that everything gets explained.

An Introduction To FPGA And CPLD - [Link]

30 May 2014

Comes with all the hardware and software you need to quickly get your FPGA project going. Now you can focus on the real engineering.

When we came up with our board’s design, we looked at what was available in other boards on the market and enhanced it.

Our kit is small, much smaller than the closest thing on the market,it’s smaller than a credit card at only 1.8 in x 3.0 in. That means you can put it inside some pretty small projects. (Here’s something to get you thinking, by 2025 the cost of putting one pound into space is expected to be just $100.)

And our kit is bread board friendly, so you can quickly connect it to a shield or to a bread board.

Now, there’s a handful of other broads with many of these features on the market, but our miniSpartan6+ costs around half of what its closest competitor does.

miniSpartan6+ : A Powerful FPGA Board and Easy to Use IDE - [Link]

10 May 2014

Detailed look at methods for driving LED matrix displays, including simple LED displays and full-colour video screen modules.

Driving LED matrix displays with an FPGA - [Link]

26 Apr 2014

ALT037

The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, the hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. The technology enables Altera to deliver up to 1.5 TeraFLOPs DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. This now gives DSP designers the choice of either fixed or floating-point modes. The floating point blocks are backwards compatible with existing designs.

Altera adds Floating Point feature to Gate Arrays - [Link]

17 Mar 2014

top

A XC6SLX9 based design with a soft CPU and USB device interface implemented in Verilog.

This features my AltOR32 OpenRISC compatible CPU running at 48MHz which hosts a cutdown USB 1.1 (Full Speed) device, SPI master and GPIO interfaces.

The nice thing about this implementation is the low chip count (only required components are the FPGA, LDOs, SPI Flash & USB PHY).

Also, as the USB 1.1 device is implemented in the FPGA rather than an external USB to serial bridge, I’m free to implement other USB class devices (such as Audio, MSD, etc).

Currently comes with USB CDC device stack (virtual COM port). RTL, SW & schematics provided.

FPGA Based ‘Bus Pirate’ clone - [Link]

1 Mar 2014

The ring counter is useful in hardware logic design such as Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA). The ring counter is also ideal in creating simple finite state machines.

The diagram is a circuit of a 4-bit twisted ring counter which can function in 4 different modes, namely: Serial-Input-Serial-Output (SISO), Serial-Input-Parallel-Output (SIPO), Parallel-Input-Serial-Output (PISO), and Parallel-Input-Parallel-Output, by applying Qo to the serial input, the resulting circuit will be a twisted ring or a Johnson Counter.  Twisted ring counters are shift registers where the output from the last flip-flop becomes the input of the first flip-flop; it will result in a closed loop circuit which recirculates the data bits around a continuous loop for every sequence state.

The circuit is composed of NAND gates, flip-flops, voltage sources, and clocking system. The NAND gates are incorporated in a Quad-2 input NAND Gate integrated circuit with part number 74ABT00D. The NAND gates receive the inputs from D0, D1, D2, and D3. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. The circuit also uses JK flip flops as the memory element. For this circuit, the dual JK flip-flop IC with part number 74HC109D is used. Two 74HC109D chips are used since the circuit needs four JK flip-flops and each IC has two JK flip-flops in it. The 74HC109 is a dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.  The set and reset are asynchronous active LOW inputs and operate independently of the clock input.  The supply voltages used to power the ICs are set at 5V for 74ABT00D IC and -1.5V for the 74ABT00D IC. The clocking system connected to the flip-flops provide synchronization pulses and timing for the circuit.

Components:

  • 74ABT00D Quad-2 input NAND Gate
  • 74HC109D Dual Positive-edge triggered JK flip-flops
  • Clocking system
  • +5V DC Voltage Source
  • -1.5V DC Voltage Source

4-bit Twisted Ring Counter using JK Flip Flops – [Link]



 
 
 

 

 

 

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