Software category

Free PADS PCB packages from Mentor/Digi-Key

by Graham Prophet @ eedesignnewseurope.com:

Two versions of the PADS software package (by Mentor, now a Siemens business) have been made available through distributor Digi-Key. Positioned as design software for “the aspiring innovator” both the free and the $499 versions include access to parts libraries and to a circuit simulator.

Free PADS PCB packages from Mentor/Digi-Key – [Link]

Mostly free engineering software

Michael Dunn @ edn.com has compiled a list of software that most enginners should be aware off.

We’re living in a golden age of software, where many useful programs are available – for free!

Let’s survey some of what’s out there that just might interest an engineering crowd like the EDN  community.

I can’t offer personal opinions on most of these packages, but I expect to hear back from you after you’ve test driven a few.

Mostly free engineering software – [Link]

New Release For EAGLE CAD with PCB Alignment Tools

Since Autodesk acquired Eagle CAD, big changes have been made to Eagle CAD. Regardless of the new licensing system using subscription model, which was a subject to criticism by a lot of users, the new management of Eagle from Autodesk has successfully added a lot of demanding features that old team failed to bring out.

Eagle 8 came with a lot of new features like BGA auto-router and “Past Block Design” tool to add a complete block of connected components both in schematic and board.

The new release 8.1.1 brought PCB alignment tool to align a group of objects in different positions; top, bottom, left, right, center, and distribute horizontally / distribute vertically.

Image Source: Autodesk Eagle’s Forum

Another improvement in eagle 8.1.1 that deserves mention is that a new category has been added to DRC (Design Rule Check) called Airewire. It’s an important improvement because airwires is one of the most common things designer should be aware of. In older Eagle releases, you should work with your eyes wide open and never forget to hit ratsnest at the end of your work and read the magic sentence in the bottom corner “Ratsnest: Nothing to do !”.

Image Source: Autodesk Eagle’s Forum

Source: Autodesk Eagle’s Forum

Exploring Eagle CAD ULPs #6 – Group-aps_v4.ULP Autoplace by Group

Welcome to the 6th post of the “Exploring Eagle CAD ULPs” series. Each post will be discussing one useful ULP in Eagle CAD.

“ULP” User Language Program is a plain text file which is written in a C­-like syntax and can be used to access the EAGLE data structures and to create a wide variety of output files. You can think about it as a plug-in for Eagle.

You can reach the posts published in this series using the following link.

In the previous post we explored Place50 ULP which places all parts of the board to the position in the schematic. Place50 moves all parts of the board, but sometimes we need to do this auto-placement for just a certain group of parts. Beside that, we can’t change the position scaling factor in Place50. Group-aps_v4 ULP overcomes these two points of limitation in Place50 ULP by doing the auto-placement by group, and having user defined position scaling and offset.

To use Group-aps_v4 ULP first download it from Autodesk website. Before running it in the schematic editor, you need to define a group of parts first.

Group-aps_v4 has a simple dialog to enter scale and offset values.

Scale is used to scale the value of original position (X and Y) of the parts in the defined group in the schematic. While X,Y offset is used to offset the final position of the part in the board after scaling it. For example, if scale was 0.5 and the position (in mil) for the part is (500,100) then is will be considered as (250,50).

Group-aps_v4 ULP originally places the group in the calculated position of the the first part. So as an output, all parts will have the same X and Y and that’s not effective. So i made a simple edit to the ULP to solve this issue. You can download the updated version N_group-aps_v4.ulp.

Know your Tool – Optimize C Code for microcontrollers

One of the talks in the “Embedded Linux Conference 2016” was about best practices to optimize C for microcontrollers. This talk deserves to be mentioned to Electronics-lab readers.

The presenter Khem Raj worked on Comcast’s (broadcasting and cable television company) reference design kit for STB, Gateway and IoT platforms.

We will cover some important points that have been suggested by the presenter:

Optimization Levels

Optimization in compilers in general (GCC is the one in Khem’s case) has different levels (5 Levels: Os, O1, O2, O3 and Og). Os is for size optimization while O1, O2 and O3 are for performance.

Optimization Levels - From Khem’s slides
Optimization Levels – From Khem’s slides

Linker

Linker which is an important tool in microcontrollers’ software toolchain, is mentioned in Khem’s talk.

Linker script is written in the linker command language and controls the memory layout of the output file (what goes where). Moreover, Linker can output a map file which is very useful when you want to track down references to symbols in the MCU memory.

Linker Script File - From Khem’s slides
Linker Script File – From Khem’s slides

Objdump

GNU GCC has a collection of binary tools; they are called (binutils); and objdump is one of them. It interleaves your assembly code with source code so you can do disassembling using it.

Variables

Talking about best practices with variables. If the concept of local, global, volatile, const and static are blurred for you, then watching this presentation will clarify them besides other important terms.

Khem also mentioned special integer types in C99; they are “fast” and “least” types. So you can allocate your variable like that:

  • Fixed width unsigned 8 bit integer uint8_t
  • Minimum width unsigned 8 bit integer uint_least8_t
  • Fastest minimum width unsigned 8 bit integer uint_fast8_t

To ensure portability of your code, Khem advised to use portable datatypes using uint{8,16,32,64}_t type declaration. This avoids effects of changing size of int type across different processors (compilers).

Using global and local variables is another concern. Khem advised to use local variable as much as possible. Global variable needs to be loaded from memory and stored back every time it is used. So if you use a global variable in a loop you will have multiple loading and storing operations.

Khem’s presentation has other tips about: array subscript Vs. pointer access, loop increments Vs. loop decrements and other stuff. Make sure to watch the presentation, all of it!
Slides

Exploring Eagle CAD ULPs #5 – Place50.ULP Place All Parts of The Board to The Position in The Schematic

Welcome to the 5th post of the “Exploring Eagle CAD ULPs” series. Each post will be about one  useful ULP in Eagle CAD.

“ULP” User Language Program is a plain text file which is written in a C­-like syntax and can be used to access the EAGLE data structures and to create a wide variety of output files. You can think about it as a plug-in for Eagle.

You can reach the posts published in this series using the following link.

In this post, we will discuss an autoplacer ULP. Normally, Eagle CAD places parts in the board without any considerations to electrical connections, and there isn’t any built-in auto-placing tool in Eagle.

Without the help of ULPs, you will need to do this task manually by moving connected parts near to each other. However, some ULPs can solve this problem ــ manual placement is a time consuming task when the PC can help us !.

Place50 ULP has a simple and smart idea. It’s an autoplacer which places all parts of the board to the position in the schematic. To use this ULP first download it from Autodesk website to run it in schematic. Running this ULP from schematic editor will generate a script file in your home directory. Now open board editor and run the script file “place.scr”.

I made a little edit to the original ULP to make the script file be saved in the same directory of the project rather than the home directory. Download it from here.

ARM Compiler 6 With A Safety Package

Developed by ARM, the latest C/C++ compiler “ARM Compiler 6” had been announced with a safety package in a move to help developers to meet functional safety requirements.

ARM Compiler 6 is based on the modern LLVM framework and Clang technology, in close collaboration with processor and architecture projects to best utilize every new hardware feature. LLVM is a set of open-source components that allow the implementation of optimizing compiler frameworks. Clang is a compiler front end for LLVM, providing support for the C and C++ programming languages.

The ARM Compiler 6 comprises the following components:

  • ARM C, C++, and GNU assembly language compiler, armclang
  • ARM and Thumb assembler, armasm
  • ARM linker, armlink
  • ARM librarian, armar
  • ARM image conversion utility, fromelf
  • supporting libraries.

ARM Compiler enables you to build applications for the ARM family of processors from C, C++, or assembly language source. So, the ARM Compiler toolchain will be a safe option for you, whether you are a semiconductor company or you just like to know that you will be covered on your ARM projects no matter what.

“ARM Compiler is already widely used in functional safety. ARM engineering has built on that expertise and further tuned the compilation toolchain for an increasingly diverse range of safety-related applications across ARM Cortex-A, -R and -M processors.”

Tony Smith, the senior director of marketing with ARM’s Development Solutions Group.

The safety package will include the certificate and related reports from TÜV SÜD confirming that ARM Compiler 6 meets the highest tool qualification levels required by ISO26262, 61508, 62304 and EN50128. This means that you can begin developing safety-related applications with ARM Compiler 6 today, while we get the final safety artifacts ready for you.

Jump Over The Limits of ARM With ExaGear Desktop

While the most of Linux programs are compiled to run on Intel x86 processors, the virtualization softwares appear to give the ability to run Intel x86 application on ARM-based Mini PC such as Raspberry Pi.

In this way, Eltechs, a high-tech startup company, had produced a new binary translator called “ExaGear Desktop”. It runs applications for the conventional desktop and server x86 processors on energy-efficient ARM CPU without recompilation.

ExaGear Desktop creates a second system known as the ‘guest’ system. Once installed, you can switch between the guest and your regular (‘host’) system using the ExaGear and exit commands. Inside the guest system, apt-get and dpkg are used to install Intel x86 software. The guest system is a transparent operation so there is no difference between running x86 applications on x86-based or ARM-based platform. It also gives you the ability to run Windows applications by installing Wine.

ExaGear is compatible with many of ARM-based Mini PCs such as Raspberry Pi 1, Raspberry Pi 2, ODROID, CubieBoard, CuBox, Utilite, Jetson TK1, Wandboard, Banana Pi etc. It also can run on Chromebook with Linux.

Compared with QEMU, another open-source virtualization software, ExaGear is  5 time faster and has  much better performance with CPU and memory as the benchmark results shown when running on Raspberry Pi 2. You can see the benchmarking details and results here.

ExaGear is available for ordering through the official website with a price range between $16.45 and $56.45 according to the hardware used. You can find more information at the product page. And it may be useful to take a look at this review.

PCB-Investigator Now Supports Browser-Based PCB Design Review

PCB-Investigator is a CAD software developed by EasyLogix for circuit board design and PCB quality assurance. Its latest version came earlier in February with a new browser interface that enables electronics assemblers to do PCB review processes without the need for local installation.

By using the ODB++ data format, PCB-Investigator creates a common database, which documents every change, and is accessible to everyone involved in the development, quality assurance and production process. With the software’s comprehensive visualization, export and import capabilities, all layout reviews are easier. Errors can be fixed earlier and prototypes can be reduced. Further improvements in version 8.0 are an improved component library with editor capability as well as clearance and creepage distance measurement.

(more…)

Export Eagle Libraries With SnapEDA

Although the new Eagle subscription model by Autodesk will bring much-needed features to the software, many users after the announcement had decided to move their work to other alternatives, such as KiCad, Altium, Cadence, etc.

One of the challenges was to convert the libraries made by Eagle to be compatible with other software programs. SnapEDA solved that by offering a new free tool that translates Eagle libraries to KiCad, Altium, OrCad and other formats.

SnapEDA is a parts library for circuit board design provides free symbols, footprints, and 3D models for millions of electronic components. The goal behind SnapEDA is to build one trusted, canonical source of electronics design content that everyone can benefit from.

To convert your Eagle library just upload your file here, then you can re-download it in any format through your uploaded models page. The video below demonstrates the converting process:

Currently, all the uploaded parts will be public on SnapEDA until the private version is released. All parts are clearly marked as user-generated content and attributed to the uploader, and can be deleted at any time.

“We are big fans of Eagle and the new changes they’re making, and are confident that the subscription model will bring much-needed features to the software. But we also understand that it is (for many) a showstopper. Hopefully this free tool is helpful to those for whom this is the case.” – SnapEDA

Try now this tool and convert your files here!