Tag Archives: eFPGA

Taking Advantage of Embedded FPGA (eFPGA)

By Geoff Tate, CEO of Flex Logix, Inc.

Whether you are designing an SoC, MCU or other chip, the one common heartache is “freezing RTL.” Up until that point, it’s no problem making a change or update, but once it’s frozen, the chip design is “locked in.” A change after that point could require a new spin that is not only costly, but can also significantly delay the chip development schedule.

Now imagine what it would be like to have no deadline to freeze RTL. What chip designer would not want that? The good news is this is now possible using embedded FPGA (eFPGA). With eFPGA, designers have the flexibility to make changes at any point in the chip development process, even in the customers’ systems. While this is beneficial to any chip design team, it is especially beneficial for applications such as data centers, networking, deep learning, artificial intelligence, aerospace and defense.

What is eFPA?

Many people think that eFPGA is the same as traditional FPGA such as those offered by Xilinx and Altera. This is not the case at all. While the technology is similar, eFPGA requires no SERDES and PHYs because on-chip signaling is very fast. Density is also very similar, although some eFPGA platforms are much better than others so designers need to do their homework and shop around for the best platform. The real difference is the users. FPGA chips are used primarily by systems companies, with some in high volume. eFPGAs are used primarily by chip companies who need to integrate a small amount of FPGA-like flexibility into their chips.

An FPGA combines an array of programmable/reconfigurable logic blocks in a programmable interconnect fabric. In an FPGA chip, the outer rim of the chip consists of a combination of GPIO, SERDES and specialized PHYs such as DDR3/4. In advanced FPGAs, the I/O ring is roughly 1/4 of the chip and the “fabric” is roughly 3/4 of the chip. The “fabric” itself is mostly interconnect in today’s FPGA chips where 20-25% of the fabric area is programmable logic and 75-80% is programmable interconnect.

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What is Embedded FPGA — Known as eFPGA

Today’s market requirements change faster than the typical development time for a new device or the ability of designers of SoCs to know. To solve this problem, FPGAs/MCUs are used so developers can change the configuration/firmware later.

As known, MCU IP is static and you can’t change the silicon design (RTL design) after fabrication. FPGA chips are used to overcome this limitation but the FPGA high cost is a concern compared to the price of the MCUs. From this point a new technology called Embedded FPGA (eFPGA) was invented. This technology can give the flexibility of allowing SoCs to be customized post-production with no high expenses.

Image courtesy of FlexLogic

The idea behind eFPGA is to embed the FPGA core to SoCs without the other components of typical FPGA chips such as: surrounding ring of GPIO,SERDES, and PHYs. This core can be customized in a post-production stage with no need to change the RTL design and manufacturing the chips again.

Image courtesy of QuickLogic

One of eFPGA use cases is an always-on sensor hub for sensor data acquisition. In this use case, the eFPGA can be used to run sensor hub at a very low power level, while the main CPU is hibernated until relevant data is available. eFPGA has other useful uses such as ,and not limited to: software reconfigurable I/O pin multiplexing and Customize GPIO and Serial Interfaces in software.

Moreover, eFPGA is expected to have a brilliant future and to be adapted widely according to the CEO of Flex Logix Technologies in an article published on Circuit Cellar magazine. That’s because of increasing mask cost: approximately $1 million for 40 nm, $2 million for 28 nm, and $4 million for 16 nm, and the need for constantly changing in standards and protocols besides application of AI and machine learning algorithms.

For more information about eFPGA, please refer to this article: Make SoCs flexible with embedded FPGA.