Tag Archives: IMEC

Imec and Cadence Tape Out Industry’s First 3nm Processor Chip

Nanoelectronics research institute IMEC and Cadence Design Systems have worked together to produce a tape-out for the industry’s first 64bit processor core as a test chip to be built in a nominal 3nm node. The tape-out project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and Cadence tools.

Cadence and Imec have created and validated GDS files using a modified Cadence tool flow. It is based on a metal stack using a 21-nm routing pitch and a 42-nm contacted poly pitch created with data from a metal layer made in an earlier experiment. The Cadence tools used include the Innovus implementation system that makes use of massively parallel computation for the physical implementation system to achieve power, performance, and area (PPA) targets. The Genus synthesis tool provides RTL synthesis that addresses FinFET process node requirements.

IMEC utilized a standard industry’s 64-bit CPU for the design with a custom 3nm standard cell library. For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.

Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec hopes to optimize the process to use a single pass in the EUV scanner. Ultimately, fabs may migrate to a planned high-numerical-aperture version of today’s EUV systems to make 3-nm chips.

Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-Han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs utilized in today’s 16-nm and finer processes.

As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at Imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.

Imex and Cadence are achieving new milestones together with this new 3nm tape-out, which can transform the future of mobile designs at advanced nodes. For more information on EUV technology and 193i technology, see the article about it here.

Prosthetics Feeling Is Now Possible With This Implantable Chip By Imec

Imec, the world-leading research and innovation hub in nano-electronics and digital technology, announced last month its prototype implantable chip that aims to give patients more intuitive control over their arm prosthetics. The thin-silicon chip is said to be world’s first for electrode density. Creating a closed-loop system for future-generation haptic prosthetics technology is the aim of researchers.

What is special about this chip?

The already available prosthestics are efficient and have their own key features; like giving amputees the ability to move their artificial arm and hand to grasp and manipulate objects. This is done by reading out signals from the person’s muscles or peripheral nerves to control electromotors in the prosthesis. Good news is that revolutionary features are coming! The future prosthetics will provide amputees with rich sensory content. This can be done by delivering precise electrical patterns to the person’s peripheral nerves using implanted electrode interfaces.

The goal behind working on this new technique is to create a new peripheral nerve interfaces with greater channel count, electrode density, and information stability according to Rizwan Bashirullah, director of the University of Florida’s IMPRESS program (Implantable Multimodal Peripheral Recording and Stimulation System)

Fabricated amazingly in a small scale!

A prototype of ultrathin (35µm) chip with a biocompatible, hermetic and flexible packaging is now available. On its surface are 64 electrodes, with a possible extension to 128. This large amount of electrodes is used for fine-grained stimulation and recording. As the short video shows, the researchers will insert the package and attach it to a nerve bundle using an attached needle which will give better results compared to other solutions usually wrapped around nerve bundles.

“Our expertise in silicon neuro-interfaces made imec a natural fit for this project, where we have reached an important milestone for future-generation haptic prosthetics,” commented Dries Braeken, R&D manager and project manager of IMPRESS at imec. “These interfaces allow a much higher density of electrodes and greater flexibility in recording and stimulating than any other technology. With the completion of this prototype and the first phase of the project, we look forward to the next phase where we will make the prototype ready for long-term implanted testing.”

The Defense Advanced Research Projects Agency’s (DARPA) Biological Technologies Office sponserd this work of University of Florida researchers under the auspices of Dr. Doug Weber through the Space and Naval Warfare Systems Center. For more details about this topic check this article.