An Arduino UNO Flash and RAM update with the ATmega2560 as DIL 28 variant.
I love the Arduino UNO with the DIL 28 ATmega328. He is easy to replace and all my projects are equipped with it. But constantly either the flash memory, the RAM or both is too small. Therefore, I have developed a replacement that provides 8 times more memory. For this I went into the microcosm of the PCB construction and impressed an ATmega2560-16CU in the smallest possible layout.
Increase Arduino UNO memory with ATmega2560 – [Link]
Technologic Systems has begun testing its first i.MX6 UL (UltraLite) based board, which is also its first computer-on-module that can work as a single board computer. The footprint of 75 x 55mm TS-4100 module features a microSD slot, onboard eMMC, a micro-USB OTG port with power support, and optional WiFi and Bluetooth. This board offers long-term support and a temperature operating range of -40 to 85°C, and ships with schematics and open source Linux images (Ubuntu 16.04 and Debian Jesse).
This board contains a low-power (4k LUT) MachX02 FPGA from Lattice Semiconductor. Technologic has improved the FPGA with an open source, programmable ZPU soft core that provides support for offloading CPU tasks as well as harder real-time on I/O interactions. The 32-bit, stack-based ZPU architecture offers a full GCC tool suite. In this implementation, it’s imbued with 8K of BlockRAM, which can be accessed by the i.MX6 UL, and has full access to all FPGA I/O.
The low-power i.MX6 UL and its power management IC are utilized to provide an efficient 300mW typical power usage. The module is equipped with 512MB to 1GB DDR3. The specification list concludes only 4GB MLC eMMC or 2GB of “robust” SLC eMMC as options, but the block diagram suggests you can load up to 64GB eMMC.
The TS-4100 is equipped with a pair of 10/100 Ethernet controllers plus LCD and I2S interfaces for media connectivity. There are also several serial and USB interfaces along with the micro-USB OTG port. Other interfaces are listed as an accelerometer, gyro, SPI, I2C, and PWM and 2 separate CAN buses.
Key specifications for the TS-4100:
512MB to 1GB DDR3 RAM
4GB MLC eMMC or 2GB SLC eMMC (possibly up to 64GB eMMC)
Wireless — 802.11 b/g/n with antenna; Bluetooth 4.0 BLE
2x 10/100 Ethernet controllers
Micro-USB OTG port (with power support)
USB 2.0 OTG (with power support)
RS232 for Linux console
SPI, I2C, 2x CAN buses
Optional FPGA/ZPU-linked 16-pin expansion header (5x DIO, 1x SPI, 1x I2C) for optional daughter cards
46x DIO (linked to FPGA)
5V input via USB or via baseboard
0.3W typical consumption
Operating temperature — -40 to 85°C
Dimensions — 75 x 55mm
Operating systems — Linux 3.14.52 (Ubuntu 16.04 and Debian Jessie)
Flash memory is one of the most widely used types of non-volatile memory. NAND Flash is designed for modern file storage which replaced old disk drives. This article provides a brief understanding of how NAND Flash technology works.
The basic storage component used in Flash memory is a modified transistor. In a standard transistor, the flow of current through a channel between two contacts is turned on by a voltage applied to the gate. The channels are separated by an insulating layer of Oxide. In a Flash storage cell, there is an extra electrically isolated gate called “floating gate”. It is added to the control gate and the channel of the modified transistor.
High voltage is applied to the control gate of The Flash cell to program it. This pushes electrons to pass through the oxide layer to the floating gate (a process known as tunneling). The presence of these trapped electrons on the floating gate changes the required voltage to turn on the transistor. Thus, a transistor with no charge on the floating gate can easily turn on at a certain voltage, representing a 1, while a programmed cell will not turn on, representing a 0.
This kind of memory is non-volatile because the floating gate is surrounded by dielectric layers, it traps the electric charge even when the power is removed. Erasing a cell reverses this process by introducing a large negative voltage to the control gate to force the electrons to tunnel out of the floating gate.
A number of cells, typically 32 to 128, are connected in a string. Strings are organized in blocks. To program cells in a block, the data is put on the bit lines and a high voltage is applied. Because programming can only change a cell from a 1 to a 0, any cells where the new data is a 1, will be left in their current state. Therefore, all the cells must be erased before writing. This process ensures that any cells that will not be programmed already contain a 1.
As explained above, each cell can store a single binary value, 0 or 1. It is also possible to inject varying amounts of charge onto the floating gate so that the cell can express multiple values. A multi-level cell (MLC) can store four different levels to represent two bits. However, the performance is reduced because of the complexity of accurate voltage controls. For the same reason, MLC Flash memory is more inclined to errors.
Although flash memory has a limited number of write-erase cycles, the high voltages cause a small amount of damage to the cells which makes them harder to read-write over time. The main drawback of using a flash memory is that it has a lifetime of about 100,000 cycles or fewer for MLC Flash.
Update your tinyAVR code to access memories when using 1-series tinyAVRs. Link here (PDF)
On tinyAVR® 1-series devices, access to Flash memory and EEPROM has been changed from that on previous tinyAVR devices. This means that existing code for writing to Flash and EEPROM on older devices must be modified in order to function properly on tinyAVR 1-series devices. This application note describes what has changed and how to adapt code to these changes.
Writing to flash and EEPROM on the tinyAVR 1-series – [Link]
Samsung Electronics has begun mass production of what the company claims to be the industry’s first 512-gigabyte (GB) embedded Universal Flash Storage (eUFS) solution for use in next-generation mobile devices. by Julien Happich @ eenewseurope.com:
The 512GB eUFS packs eight of Samsung’s latest 64-layer 512-gigabit (Gb) V-NAND chips together with a controller chip, doubling the density of Samsung’s previous 48-layer V-NAND-based 256GB eUFS in the same amount of space as the 256GB package. The new high-capacity eUFS enables a flagship smartphone to store approximately 130 4K Ultra HD (3840×2160) video clips of a 10-minute duration. To maximize the performance and energy efficiency of the new 512GB eUFS, Samsung has introduced a new set of proprietary technologies. The 512GB eUFS’ controller chip speeds up the mapping process for converting logical block addresses to those of physical blocks. With its sequential read and writes reaching up to 860 megabytes per second (MB/s) and 255MB/s respectively, the 512GB embedded memory enables transferring a 5GB-equivalent full HD video clip to an SSD in about six seconds, over eight times faster than a typical microSD card.
512Gbyte embedded universal flash memory in production – [Link]
Microchip introduced a new 64Mbit Serial Quad I/O™ memory device—SST26WF064C with proprietary SuperFlash® technology.The SST26WF064C writes with a single power supply of 1.65-1.95V and significantly lower power consumption. This makes it ideal for wireless, mobile, and battery-powered applications.
This 64Mbit memory device also features DTR or Dual Transfer Rate technology. DTR lets the user access data of the chip on both rising and falling edges of the clock, reducing overall data access time and power consumption significantly. The SST26WF064C utilizes a 4-bit multiplexed I/O serial interface to boost performance while maintaining the tiny form factor of standard serial flash devices.
Microchip’s high-performance CMOS SuperFlash technology provides the fastest chip erase time, consequently, reduces overall power consumption. It also improves performance and reliability of the memory chip. The SST26WF064C’s typical chip-erase time is 35-50 milliseconds, where other chips take nearly 30 seconds to be completely erased.
This chip combines a hardware controlled RESET function which is not present in common flash chips available in the market due to their limited pin count. In SST26WF064C, the user can program the HOLD pin to use for the RESET function. This feature lets the host microcontroller to reset the chip by sending a pulse to it.
SST26WF064C supports full command-set compatibility with traditional Serial Peripheral Interface (SPI) protocol. Operating at frequencies reaching 104 MHz, the SST26WF064C enables minimum latency execute-in-place (XIP) capability without the need for code shadowing on a SRAM. To learn about code shadowing, read this article.
The key features of the SST26WF064C are:
Single Voltage Read and Write Operations – 1.65-1.95V
Serial Interface Architecture
High-Speed Clock Frequency (104 MHz max.)
Low Power Consumption
Fast Erase Time
Flexible Erase Capability
Suspend Program or Erase operation to access another block/sector
Software and Hardware Reset mode
One-Time Programmable (OTP) 2KByte Secure ID
64 bit unique, factory pre-programmed identifier
To learn more about this memory chip or to purchase some, visit http://www.microchip.com/wwwproducts/en/SST26WF064C.
The need for larger memory storage for smartphones will never stop, especially with the continuous development of larger and stronger applications. This need is always pushing semiconductor manufacturers to keep trying to fit as much bits as possible in smaller volumes and with lower costs.
To achieve this, memory chips are now growing in three dimensions instead of two. Recently, Toshiba has developed a new 96-layer BiCS 3D flash memory device with a storage capacity of 32 GB. The new device meets market demands and performance specifications for applications that include enterprise and consumer SSD, smartphones, tablets and memory cards.
This memory chip was built with three bits per cell, known as triple-level cell (TLC) technology. Stacking layers and manufacturing process increase the capacity of each chip with 40% per unit size. They also reduce the cost per bit, and increase the manufacturability of memory capacity per silicon wafer.
In order to add more layers to the chip, Toshiba is working on increasing the number of bits in every cell. In the near future, it will apply its new 96-layer process technology to larger capacity products, such as 64 GB. It will also develop chips with QLC (quadruple-level cell) technology.
By stacking 64 layers of QLCs, the engineers at Toshiba have created a 96-gigabyte device. Integrating 16 of them in one package will achieve a capacity of 1.5 TB, that corresponds to 12 trillion bits.
If you are interested, you can check these out at the 2017 Flash Memory Summit in Santa Clara, California from August 7-10.
MCUs are called microcontrollers because they embed a CPU, memory and I/O units in one package. Apparently, today’s MCUs are full of peripherals and in most cases they are not used in the application, and from an engineering point of view this is a waste of money and energy, but on the other hand, for developers and consumers it’s about programmability and flexibility.
Rakesh Kumar a University of Illinois electrical and computer engineering professor and John Sartori a University of Minnesota assistant professor tried to prove that processors are overdesigned for most applications.
Kumar and his colleagues did 15 ordinary MCU applications using openMSP430 microcontroller with bare metal and RTOS approach (both are tested in their study). Surprisingly, the results showed that all of these applications needed no more than 60 percent of the gates. Therefore, smaller MCUs can be used (cheaper and less power consuming). As stated by Sartori, “a lot of logic that can be completely eliminated, and the software still works perfectly”.
In the image above the analysis of unused gates for two applications: Interpolation FIR filter and Scrambled Interpolation FIR. The red dots are the used gates and gray ones are the not used ones.
The research team called the optimum MCU the “Bespoke Processor”, and described the process “like a black box. Input the app, and it outputs the processor design.” says Kumar.
SK Hynix Incorporated introduced the world’s first 72-Layer 256Gb (Gigabit) 3D (Three-Dimensional) NAND Flash based on its TLC (Triple-Level Cell) arrays and own technologies. This company also launched 6-Layer 128Gb 3D NAND chips in April 2016 and has been mass producing 48-Layer 256Gb 3D NAND chips since November 2016. Within 5 months the researchers in SK Hynix developed the new technology of producing 72-layer 3D NAND flash.
The technological achievement of this 72-Layer 3D NAND is compared to the difficulty of building approximately 4 billion 72-storied skyscrapers on a single dime. Well, now the question maybe, “Is the difficulty and complexity of this new technology giving any remarkable outcome?”. The answer is a big YES. The 72-layer NAND is said to stack 1.5 times more cells than the 48-layer, achieving 30% more efficiency in productivity and 20% higher read/write performance than a 48-layer 3D NAND chip, the predecessor of this 72-layer .D 256Gb NAND flash.
With this new chips having 30% more efficiency in productivity and 20% higher performance, SK Hynix has been currently developing NAND Flash solutions such as SSD (Solid State Drive) and storage for mobile devices such as smartphones. Having high reliability and low power consumption this 3D NAND flash should be an ideal solution for storage problems of mobile devices.
SK Hynix plans to expand the usage of the product to SSDs and mobile gadgets to further improve its business structure weighted towards DRAM. The vice president Jong Ho Kim said in the press release,
With the introduction of this industry’s highest productivity 3D NAND, SK Hynix will mass produce the 256Gb 3D NAND in the second half of this year to provide this to worldwide business clients for optimum use in storage solutions
According to a market research, 3D NAND flash demand is rapidly increasing across AI(Artificial Intelligence), big data, and cloud storage. The research by Gartner says that NAND Flash market revenue is expected to total USD 46.5 billion in this year and it will grow up to an amount of USD 56.5 billion in 2021.
Toshiba has added a 512-Gbit (64-Gbyte), 64-layer flash memory device that employs 3-bit-per-cell TLC (triple-level cell) technology to its BiCS Flash product line. This technology will allow the development of 1-terabyte memory chips for use in enterprise and consumer solid-state drives.