Update your tinyAVR code to access memories when using 1-series tinyAVRs. Link here (PDF)
On tinyAVR® 1-series devices, access to Flash memory and EEPROM has been changed from that on previous tinyAVR devices. This means that existing code for writing to Flash and EEPROM on older devices must be modified in order to function properly on tinyAVR 1-series devices. This application note describes what has changed and how to adapt code to these changes.
Writing to flash and EEPROM on the tinyAVR 1-series – [Link]
Samsung Electronics has begun mass production of what the company claims to be the industry’s first 512-gigabyte (GB) embedded Universal Flash Storage (eUFS) solution for use in next-generation mobile devices. by Julien Happich @ eenewseurope.com:
The 512GB eUFS packs eight of Samsung’s latest 64-layer 512-gigabit (Gb) V-NAND chips together with a controller chip, doubling the density of Samsung’s previous 48-layer V-NAND-based 256GB eUFS in the same amount of space as the 256GB package. The new high-capacity eUFS enables a flagship smartphone to store approximately 130 4K Ultra HD (3840×2160) video clips of a 10-minute duration. To maximize the performance and energy efficiency of the new 512GB eUFS, Samsung has introduced a new set of proprietary technologies. The 512GB eUFS’ controller chip speeds up the mapping process for converting logical block addresses to those of physical blocks. With its sequential read and writes reaching up to 860 megabytes per second (MB/s) and 255MB/s respectively, the 512GB embedded memory enables transferring a 5GB-equivalent full HD video clip to an SSD in about six seconds, over eight times faster than a typical microSD card.
512Gbyte embedded universal flash memory in production – [Link]
Microchip introduced a new 64Mbit Serial Quad I/O™ memory device—SST26WF064C with proprietary SuperFlash® technology.The SST26WF064C writes with a single power supply of 1.65-1.95V and significantly lower power consumption. This makes it ideal for wireless, mobile, and battery-powered applications.
This 64Mbit memory device also features DTR or Dual Transfer Rate technology. DTR lets the user access data of the chip on both rising and falling edges of the clock, reducing overall data access time and power consumption significantly. The SST26WF064C utilizes a 4-bit multiplexed I/O serial interface to boost performance while maintaining the tiny form factor of standard serial flash devices.
Microchip’s high-performance CMOS SuperFlash technology provides the fastest chip erase time, consequently, reduces overall power consumption. It also improves performance and reliability of the memory chip. The SST26WF064C’s typical chip-erase time is 35-50 milliseconds, where other chips take nearly 30 seconds to be completely erased.
This chip combines a hardware controlled RESET function which is not present in common flash chips available in the market due to their limited pin count. In SST26WF064C, the user can program the HOLD pin to use for the RESET function. This feature lets the host microcontroller to reset the chip by sending a pulse to it.
SST26WF064C supports full command-set compatibility with traditional Serial Peripheral Interface (SPI) protocol. Operating at frequencies reaching 104 MHz, the SST26WF064C enables minimum latency execute-in-place (XIP) capability without the need for code shadowing on a SRAM. To learn about code shadowing, read this article.
The key features of the SST26WF064C are:
Single Voltage Read and Write Operations – 1.65-1.95V
Serial Interface Architecture
High-Speed Clock Frequency (104 MHz max.)
Low Power Consumption
Fast Erase Time
Flexible Erase Capability
Suspend Program or Erase operation to access another block/sector
Software and Hardware Reset mode
One-Time Programmable (OTP) 2KByte Secure ID
64 bit unique, factory pre-programmed identifier
To learn more about this memory chip or to purchase some, visit http://www.microchip.com/wwwproducts/en/SST26WF064C.
The need for larger memory storage for smartphones will never stop, especially with the continuous development of larger and stronger applications. This need is always pushing semiconductor manufacturers to keep trying to fit as much bits as possible in smaller volumes and with lower costs.
To achieve this, memory chips are now growing in three dimensions instead of two. Recently, Toshiba has developed a new 96-layer BiCS 3D flash memory device with a storage capacity of 32 GB. The new device meets market demands and performance specifications for applications that include enterprise and consumer SSD, smartphones, tablets and memory cards.
This memory chip was built with three bits per cell, known as triple-level cell (TLC) technology. Stacking layers and manufacturing process increase the capacity of each chip with 40% per unit size. They also reduce the cost per bit, and increase the manufacturability of memory capacity per silicon wafer.
In order to add more layers to the chip, Toshiba is working on increasing the number of bits in every cell. In the near future, it will apply its new 96-layer process technology to larger capacity products, such as 64 GB. It will also develop chips with QLC (quadruple-level cell) technology.
By stacking 64 layers of QLCs, the engineers at Toshiba have created a 96-gigabyte device. Integrating 16 of them in one package will achieve a capacity of 1.5 TB, that corresponds to 12 trillion bits.
If you are interested, you can check these out at the 2017 Flash Memory Summit in Santa Clara, California from August 7-10.
MCUs are called microcontrollers because they embed a CPU, memory and I/O units in one package. Apparently, today’s MCUs are full of peripherals and in most cases they are not used in the application, and from an engineering point of view this is a waste of money and energy, but on the other hand, for developers and consumers it’s about programmability and flexibility.
Rakesh Kumar a University of Illinois electrical and computer engineering professor and John Sartori a University of Minnesota assistant professor tried to prove that processors are overdesigned for most applications.
Kumar and his colleagues did 15 ordinary MCU applications using openMSP430 microcontroller with bare metal and RTOS approach (both are tested in their study). Surprisingly, the results showed that all of these applications needed no more than 60 percent of the gates. Therefore, smaller MCUs can be used (cheaper and less power consuming). As stated by Sartori, “a lot of logic that can be completely eliminated, and the software still works perfectly”.
In the image above the analysis of unused gates for two applications: Interpolation FIR filter and Scrambled Interpolation FIR. The red dots are the used gates and gray ones are the not used ones.
The research team called the optimum MCU the “Bespoke Processor”, and described the process “like a black box. Input the app, and it outputs the processor design.” says Kumar.
SK Hynix Incorporated introduced the world’s first 72-Layer 256Gb (Gigabit) 3D (Three-Dimensional) NAND Flash based on its TLC (Triple-Level Cell) arrays and own technologies. This company also launched 6-Layer 128Gb 3D NAND chips in April 2016 and has been mass producing 48-Layer 256Gb 3D NAND chips since November 2016. Within 5 months the researchers in SK Hynix developed the new technology of producing 72-layer 3D NAND flash.
The technological achievement of this 72-Layer 3D NAND is compared to the difficulty of building approximately 4 billion 72-storied skyscrapers on a single dime. Well, now the question maybe, “Is the difficulty and complexity of this new technology giving any remarkable outcome?”. The answer is a big YES. The 72-layer NAND is said to stack 1.5 times more cells than the 48-layer, achieving 30% more efficiency in productivity and 20% higher read/write performance than a 48-layer 3D NAND chip, the predecessor of this 72-layer .D 256Gb NAND flash.
With this new chips having 30% more efficiency in productivity and 20% higher performance, SK Hynix has been currently developing NAND Flash solutions such as SSD (Solid State Drive) and storage for mobile devices such as smartphones. Having high reliability and low power consumption this 3D NAND flash should be an ideal solution for storage problems of mobile devices.
SK Hynix plans to expand the usage of the product to SSDs and mobile gadgets to further improve its business structure weighted towards DRAM. The vice president Jong Ho Kim said in the press release,
With the introduction of this industry’s highest productivity 3D NAND, SK Hynix will mass produce the 256Gb 3D NAND in the second half of this year to provide this to worldwide business clients for optimum use in storage solutions
According to a market research, 3D NAND flash demand is rapidly increasing across AI(Artificial Intelligence), big data, and cloud storage. The research by Gartner says that NAND Flash market revenue is expected to total USD 46.5 billion in this year and it will grow up to an amount of USD 56.5 billion in 2021.
Toshiba has added a 512-Gbit (64-Gbyte), 64-layer flash memory device that employs 3-bit-per-cell TLC (triple-level cell) technology to its BiCS Flash product line. This technology will allow the development of 1-terabyte memory chips for use in enterprise and consumer solid-state drives.
The American manufacturer of analog and mixed-signal integrated circuits, Maxim Integrated, has developed a new serial EEPROM memory that operates from single-contact 1-wire interface.
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM organized as 80 memory pages of 256 bits each. An additional page is set aside for control functions. Data is written to a 32-byte scratchpad, verified, and then copied to the EEPROM memory.
The 1-Wire is a device communications bus system that provides low-speed data, signaling, and power over a single conductor. This technology uses only two wires; data and ground. It is similar in concept to I²C, but with lower data rates and longer range. It is typically used to communicate with small inexpensive devices such as digital thermometers and weather instruments.
20480 Bits of Nonvolatile (NV) EEPROM Partitioned into Eighty 256-Bit Pages
Individual 8-Page Groups of Memory Pages (Blocks) can be Permanently Write Protected or Put in OTP EPROM-Emulation Mode (“Write to 0”)
Read and Write Access Highly Backward-Compatible to Legacy Devices (e.g., DS2433)
256-Bit Scratchpad with Strict Read/Write Protocols Ensures Integrity of Data Transfer
200k Write/Erase Cycle Endurance at +25°C
Unique Factory-Programmed 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Part Identity
Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise
Communicates to Host at 15.4kbps or 90kbps Using 1-Wire Protocol
Blocks of eight memory pages can be write-protected or put in EPROM-Emulation mode, where bits can only be changed from a 1 to a 0 state. The life-expectancy of the DS28EC20 is specified at more that 200 k erase/write cycles at 25 °C. The I/O pin has IEC 1000-4-2 Level 4 ESD protections (8 kV contact, 15 kV air).
Applications that can use the DS28EC20:
Card/Module Identification in Rack-Based Systems
IEEE 1451.4 Sensors
Ink and Toner Cartridge ID
Medical and Industrial Sensor Identification/Calibration
Ordering DS28EC20 is available for about $1.7 per chip through Maxim website. You can also get design resources and technical documents of the chip.
Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor.
The MB85AS4MT is an SPI-interface ReRAM product that operates with a wide range of power supply voltage, from 1.65V to 3.6V. It features an extremely small average current in read operations of 0.2mA at a maximum operating frequency of 5MHz.
It is optimal for battery operated wearable devices and medical devices such as hearing aids, which require high density, low power consumption electronic components.
Memory Density (configuration): 4 Mbit (512K words x 8 bits)
Write cycle time (256 byte page): 16ms (with 100% data inversion)
Data retention: 10 years (up to 85°C)
Package: 209 mil 8-pin SOP
This figure shows the block diagram of the chip:
MB85AS4MT is suitable for lots of applications like medical devices, and IoT devices such as meters and sensors. In addition, the chip has the industry’s lowest power consumption for read operations in non-volatile memory.
Piers Finlayson shares his adventures in programming the ESP8266 to access 16MB flash:
To put this in context, the original ESP8266 modules (such as the ESP-01) offered 512KB of flash, with the more recent ones (ESP-07) 1MB and then 4MB. The maximum addressable flash memory of the ESP8266 is 16MB according to the datasheet. (The ESP32 offers up to 4 x 16MB of flash.)
I don’t have a particular need for > 4MB flash (otb-iot currently only requires and supports 4MB) but my interest was tweaked in the larger flash chips, so I thought I’d give it a go. I’ve experience of replacing flash chips from older modules to upgrade them from 1MB to 4MB, so figured 16MB would be the same.