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indulis

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Posts posted by indulis

  1. While I've never designed an iron core transformer, I have designed more ferrite core transformers than I care to remember. Ferrite core transformers are typically 98% efficient. If core losses are any higher, it's considered a bad design. Core loss is a function of frequency and volume (and this is stupid... in KW/M^3... I've NEVER seen a one cubic meter ferrite core). Then theres skin affect (not a big problem at 60Hz, but at 500KHz that's a different story), eddy current losses, I^2*R losses, coupling losses if it's not wound well. Voltage, current , inductance and power are all proportional to the turns ratio.

  2. That's not necessarily true. The power supply spec's don't mention what kind of current limit the supply has... constant power, foldback, hic-up etc. True, the supply with the highest output voltage would supply ALL the current until it's voltage started to drop. It's voltage drop would stop when it reaches the voltage of the second supply and then the parallel supply would start to supply current as well until it reached current limit and then both supplies would drop together. While the current sharing isn't equal, they are sharing. If the current limit is hic-up or latching, your out of luck.

    As for capacitors I=C*dV/dt , so (I*t)/C=V
    How much voltage drop can you tolerate?

    Even a lead acid batteries voltage will drop when you start to draw current... how much is directly related to how much current you draw.

  3. There are many factors to consider. What is the input voltage? What is the output voltage? How much current? Voltage mode or current mode? Continious or discontinious?

    Flyback transformers aren't transformers at all, they are coupled inductors. The number of turns is inversely proportional to flux density. 3 turns could work if you have the right core cross section, gap and core material. I haven't calculated one "manually" in while, let me do some digging.

    I can tell you that all that everything your looking for can be derived from

    P=1/2 * L* I^2*F   and   E=L* di/dt

  4. Hi Kevin

    Just got back from a 10 day holiday myself.

    Forget Q3, R19 and 20. That part of the circuit only controls the D12 indicator (LED). It has nothing to do with current regulation or the gain. U3 is configured (when active) like a gain limited integrator. For simplicity just think of it as some resistance (impedance) that is in parallel with C8. C8 controls the rate at which the output of U3 changes, make C8 bigger and the dv/dt at the output of U3 will be slower, make the cap smaller and the output will swing faster. All of the other stuff in the loop just reduces the gain and for DC purposes can be thought of as a resistor (the loop also has AC gain). The transfer function for the loop is quite complex and I have no desire to "hurt my brain" that much trying to derive it. For this circuit it

    post-14697-14279143403946_thumb.jpg

    post-14697-14279143404234_thumb.jpg

  5. Quote from: indulis on February 14, 2007, 02:58:47 PM
    WHAT WILL THE OUTPUT VOLTAGE OF THE COMPARATOR BE??
    It will probably oscillate.
    Its output will be floating if the load current is less than the set amount of current regulation.
    Its output voltage will drop just low enough to regulate the current if the load current is higher than the set amount of current regulation.

    If it's below the current limit setpoint it WILL NOT oscillate. The only thing a open collector collector can do is "pull-down" if it's active, and it's not active in this state, so the voltage at the output pin will float to around one diode drop, or somewhat less, below the U2 pin 3 voltage. This isn't because the comparator has an output, it's the value of the U2 pin 3 nodal voltage.  

    Quote
    WHAT WILL THE COMPARATOR OUTPUT VOLTAGE BE AS WE ADJUST THE SUPPLY OUTPUT VOLTAGE?
    If it is not regulating the current then its output is either oscillating or floating.

    The comparator has NO ability to regulate the current, it can only limit it. If it's not in current limit, it will float to/track the U2 pin 3 voltage, again around one diode drop, or somewhat less. The "somewhat less stems from the amount of leakage current in the D9 diode.


    Quote
    IS THE COMPARATORS GAIN GOING TO MAKE A DIFFERENCE AS TO WHAT THE COMPARATORS OUTPUT VOLTAGE WILL BE?
    Its very high voltage gain of typically 200,000 makes the current regulation very precise. If its gain is much less (100?) then you would notice that the regulated current amount would change a little if the load's resistance changed.

    The gain will not make ANY difference whatsoever... the comparator only has two states. It CAN NOT be made to behave like a op-amp! Having a high gain isn't going to change the threshold level, however, the "window of uncertainty" will get smaller... i.e. for a 1 volt threshold and a lower gain unit might have a window of 1V

  6. I don't know what is... either I don't know how to ask a question, you can't understand my question, you don't know how to answer my question or I can't understand your reply. Sorry,to me, your answers don't address my questions. Fine, so the intellectual route didn't work, let's try a practical example instead.

    Let's take the 0-30V power supply project schematic and for the sake of clarity, remove all the indicator components Q3, R20, R19 etc. and also C8. Now let's replace U3 with a LM393 comparator. The unit will function just fine, and we lte's say we can live with the current limit hic-up

  7. More smoke and mirrors

    Where do you see a question that asks that you

    ...prove or justify why the manufacturer of an LM393 comparator specifies that it has a voltage gain of typically 200,000
    ?

    For some reason you decline to explain why you think the open collector LM393 works the way you think it does...
    its output would be saturated at the positive supply voltage or at ground
    ... not true, with nothing connected to the output, it either FLOATS, or is pulled down to the MINUS RAIL... that's it, no other choices!! Can the output be at Vcc or ground... yes, but that's missleading and doesn't give you the "general case" fpr how it works. You also make no attempt to rationalize why gain has somethig to do with what the output voltage will be... IT DOESN'T... for the reasons above.
  8. By perpetuating your  "smoke and mirror" answers, you demonstrate your "real knowledge" of the subject!! Those that know, know... unfortunate for those trying to learn.

    Statements that try to link open loop voltage gain to what level a open collector comparator will go is pure BS!!

    Rambling on about

    The voltage gain is too high in a comparator to use its full open-loop gain with slowly changing inputs. It will amplify its input offset voltage and amplify its internal and external noise. It will probably oscillate due to the input picking up the signal from its output.

    So hysteresis is used in a comparator circuit to provide a snap-action to its switching. Then noise and oscillation are avoided but the sensitivity is much less.


    in no way attemps to justify or prove your statement to be true!!

    I've said it before... you have a great deal of practical knowledge to share and many appreciate and benifit from it... including myself on some topics, but be careful when you step beyond your own boundaries of knowledge... people that REALY know may be reading!!



  9. Guru

    I already know the answers to the questions I asked!!!
    I ask them because of statements like...

    An LM393 dual comparator has a typical input offset voltage of 1mV (5mV max) and a typical voltage gain of 200,000. Its output would try to be 200V! Its output would be saturated at the positive supply voltage or at ground.


    You state that it's output would try to be 200V? I don't think so...even it were to have a Vcc of 1000V!!! You also imply that it's gain is related somehow to what the output voltage will be... nope, not happening!!!

    The gain number is useful for one thing however, calculating the "window of uncertanty" as to when the comparator wil "flip".

    The point is that this open collector comparators gain has ABSOLUTLY NOTHING to do with how high the output voltage will go!!!

    Your the one applying linear properties to non-linear deveices... not me!!
  10. Kevin

    You say you understand how the "voltage loop" functions... good!! Looking at just the voltage loop, consider the function of D9. It's connected to the U2 pin 3 node, and the voltage at this node is what controls the output voltage. Once the voltage on the the cathode of D9 falls (is pulled down) a "diode drop" below the "programed voltage" on U2 pin 3 voltage, the "clamping action" will start. At this point, the voltage on the cathode has taken over control of the output voltage. The lower the cathode voltage goes the lower the output voltage goes. 

    Consider what can change the current through the load. If you have a fixed load, and the output voltage is going down,  the current  flowing through the load will also go down. If you have a fixed output voltage, changing the load will cause a change in the output current... decrease the load resistance, current goes up and increasing the load restistance makes the current go down (Ohms Law).

    Back to the circuit... say you set the output voltage to some value. That will equate to some voltage at U2 pin 3. Now, if you were to connect a variable power supply to the cathode of D9 and the votlage of that supply was set to be more than a diode drop above the nodal voltage at U2 pin 3 (or a voltage like a opamp at it's + rail) , it would have no affect because the diode is back biased (it's off). But if you were to start decreasing that supply connected to D9 at some piont the diode will turn on and "clamp" the U2 nodal value to that voltage and cause a decrease in the output voltage. I hope you can rationalize this action in your head.

    Next... R7 in this circuit, by ohms law, developes a voltage across it that is propotional to the current that is flowing in the output (a.k.a. current sense resistor). The more current that flows, the bigger the voltage drop. Now we're back to U3... the arm of P2 applies a reference voltage to U3 pin 3, so as long as the voltage on U3 pin 2 is below that value, U3 looks like a comparator at it's + rail. As the load current is increased, the voltage across R7 increases until the voltage on U3 pin 2 goes just a little higher than the voltage on pin 3 and the output comes off the rail and starts down. You ask how far will it come down... the output of U3 will go down to such a value that the output voltage is reduced enough to cause the voltage drop across R7 to make the voltage at U3 pin 2 be EXACTLY the same as the voltage on pin 3.

    Does this help?



  11. It depends on the input offset voltage of the comparator.
    An LM393 dual comparator has a typical input offset voltage of 1mV (5mV max) and a typical voltage gain of 200,000. Its output would try to be 200V! Its output would be saturated at the positive supply voltage or at ground. If you use a comparator with zero input offset voltage then its output would be full of full-output square-waves noise due to its extremely high voltage gain.




    It depends on the voltage gain of the comparator and on its supply voltage.
    An LM393 dual comparator has a minimum voltage gain of 50,000. So for its output to change 15V then the voltage between its inputs must be 15V/50,000= 300uV.

    Its typical voltage gain is 200,000. Then the input must be only 75uV. But such low levels would be covered up with noise.



    The LM393 is an open collector device!!!

    guru, you may want to clear up a few things in your statements above, in regards to gain and open collector devices, so that walid doesn't get the wrong idea!!
  12. Let's see... how can I explain this...

    If the output of a device (in this case the opamp U3) can somehow influence the levels at it's input pin(s), it's feedback.

    Because the voltage level at U3 pin 6 can infuence/control the voltage on U3 pin 2, all the elements in that string are part of te feedback. Since the load is what's causing the current limit circuit  (sorry, current regulator) to become active, yes, the load should be an element of the loop.

    I'm afraid that my days of writing transfer functions with that many variables is long gone (killed off those brain cells LONG AGO)!!! Aside from an academic exercise, why would you want to know the gain? If for some reason I "had to know", I'd run it through a simulator.

    I'm currently looking hard at the LED branch since R19, R20, Q3, R22, D12 AND R7 would make a feedback loop.


    How can any of those components "control/change" the voltage on the input pins to U3? They can't, so they are not part of U3's feedback. Those components only control an indicator.  For the sake of argument, lets rationalize it was in the loop. For that to be true, the current flowing thru D12 (LED) would have to go back towards R7... it doesn't, it flow towards C1. In fact, you could rip out all those components and the circuit would work just fine!!

    If your having trouble understanding how the circuit works, break it up into parts. For example, redraw the schematic without D12, R22,Q3, R19, R20, C8, U3, R17, R21, P2, R17 and D9. Look only at the "voltage loop", then add in the other suff. BTW... guess what, that circuit will work just fine with all those components removed, you just won't have "current limit".
  13. kcc

    You are half right...

    U3 "looks" like a comparator while it's not active. When U3 becomes active it behaves like a linear amplifier. At first glance, most would call it an integrator.

    It does have a feedback loop... it's just a "big one" that includes D9, U2, R15, Q2, Q4 and R7.

    The current limit pot set's a "reference" for U3. While the output current hasn't reached the the "setpoint", U3 indeed behaves like a comparator, sitting at the positive rail.  As the output current increases, so does the voltage drop across R7. When the voltage at the negative input of U3, pin 2, reaches the "setpoint" the output comes out of the + rail and starts to go towards is minus rail. The rate at which it does this is controlled by the integrating cap C8 (C8 is also feedback). The gain of U3 in this circuit isn't as high as you might think when it's "active" and not sitting at the positive rail!! As the output falls, D9, a clamping diode, starts to pull down U2 pin 3, but the voltage at pin 3 is what controls the output voltage. So as the load tries to draw more current,  U2 pin 3 is pulled lower and lower. This in turn starts to turn off Q4... via Q2. So, as the load tries to draw more current the output voltage will be reduced, just enough, such that both inputs to U3 are at held at the same voltage (feedback).

  14. This topic was around before but disappeared for some reason...

    OK... one more time, the 3525 is an "old" PWM. There are better ones out there for buck converters. The last schematic that was posted was also a little different. For starters, pins 11 & 14 should be going to the driver and pins 12 & 13 want to go to some fixed voltage (Vref maybe) NOT the R2, MOSFET drain node. This is a switching node... voltage goes from +15V to gnd here. You have pins 6 & 7 shorted by R6.

    Maybe a "general" explanation as to how these things work is in order...

    This is a voltage mode controller, it has an oscillator internally which generates a ramp waveform signal whose frequency is set by Rt and Ct . An "error" voltage is fed into pin 2 (here you have the error amp pin 9 connected to pin 1... unity gain configuration a.k.a. buffer. This signal is what controles the PWM action... higher voltage, bigger duty cycle, lower voltage, smaller duty cycle. The leading edge of the clock starts the whole cycle, at which time the "output is enabled... then a comparator monitors the ramp amplitude compared to the error voltage on pin 2... when the ramp reaches the error voltage,  the output turns off and the "ramp" finishes it's cycle and the whole thing starts over again. The key here is to understand that as the error voltage is changed, it is directly propotional to the duty cycle. You make the error voltage a little higher, it take longer for the ramp to get to the error voltage level so the output stays on longer. Make the error voltage smaller, and the ramp voltage "gets there" sooner, so the output shuts off sooner and the duty cycle is reduced... there you pretty much have it ... PWM action.

    Look at your circuit again... why would you connect the voltage divider that "simulates" your error voltage to the Rt and Ct pins... ground would be a better choice. You don't need the current sense circuitry to start playing with this chip. Tie pin 4 & 5 to ground. Pin 4 (- input) has a  -200mV offset so that should keep the current limit comparator output high and out of the circuit for now. Once you have the rest of the test circuit running you can introduce the current limit function and see how it can "limit" the duty cycle.

    Good luck!!

    Oh... one more thing, you need a pull down resistor for the driver input... otherwise it's floating in space when it's supposed to be off.

  15. Just about all DC-DC's have a input range... for example our 5V input models have a range of 4.5V to 9V. 12V models work from 9V to 18V, 24V models work from 18v to 36V and 48V models work from 36V to 75V. That's the nice thing about them.


    http://store.cd4power.com/cgi-bin/cd4power.storefront/45c9c2d5009d863e271d0c9f894206e3/Catalog/1172?nominalvolts=5&current=1.000+1.999&Output_Voltage=12&SEARCH=View...

  16. I was taking about the difference between opamps and comparators in general, not specficic part numbers.

    It is the frequency compensation capacitor in the opamp that causes its slew rate to be so slow.


    What I said was
    Can compensation make a opamp switch slow??? Yes it can, but  it's not automatic, you you have to select a value (LARGE) on purpose for that to happen. Then, slow is a relative term, how slow is slow?


    Are you suggesting that a opamp can't be compensated such that it's "fast"?
  17. There a bit more difference between the two than just that...

    Can compensation make a opamp switch slow??? Yes it can, but  it's not automatic, you you have to select a value (LARGE) on purpose for that to happen. Then, slow is a relative term, how slow is slow? One reason why opamps make lousy "fast" comparators is because you make the output saturate and it take time to come out of saturation, it's not exclusively because of compensation.

  18. Just apply the following to get the "general idea" of how they work

    1) the inputs to the opamp have infinte impedance... this means no current will flow into of out of an input.

    2) the output has zero impedance... this basically means it could supply infinte current

    3) the output will do whatever it has too to make both inputs the same (voltage)

    4) then as guru said, apply ohms law.

    For example

    take a opamp with a 1K input resistor to the negative input and a 10K resistor from the negative input to the output (feedback).  The 1K is connected to a 10V source and the positve input is connected to ground.

    Since the positive input is a ground (0V) the negative input wants to be a 0V and the output will do what ever it can to make that happen. So, if the negative input has to be at 0V, that means that the 1K has 10V across it and 10mA is flowing from the source towards the opamp. Since no current can flow into, or out of the input, all of it must flow through the feedback resistor. With 10mA flowing through 10K, that 100V, so if the negative input end of the resostor is at 0V and there is 100V across the feedback resistor, then the output must be at -100V.

    If you apply this thought process, you can solve any DC opamp circuit. If you add "C's & L's" it's a bit more complicated.

  19. Yes... we (where I work) have a flyback DC-DC converter (voltage mode) design that uses a 556. It's configured like Fig 6 in that app's note and the feedback is fed into the control pin. The only problem is that the frequency isn't constant. We use the other half of the 556 as a one-shot for the current limit hic-up time-out. You could do this with just about any voltage mode PWM.

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