login
nickagian
-
Posts
45 -
Joined
-
Last visited
Never
Content Type
Profiles
Forums
Events
Posts posted by nickagian
-
-
Yeap... I have to design a whole 2-stage CMOS OpAmp... and still haven`t find a solution.
-
-
Ooops, yes, I have forgotten to write it...I use the 9.2 Release!
-
Can anybody help me with the following circuit? As you can see it is about a CMOS OpAmp, with cascode input stage. I want to find a way to bias M3,M4 (Vb) but until now I cannot manage it. Can anybody suggest me a solution for biasing and how to calculate it (I mean the W/L ratio of the MOSFETs used, considering that I want a current of 1.5mA on both M1 and M2 tails and a bias voltage Vb of about 2V).
-
Hello everybody! I have to complete a design of an OpAmp using CMOS technology and the given model for the nMOS transistors is the following:
.model Mn NMOS(LEVEL=2 LD=0.1e-6 VTO=0.77 KP=77e-6 GAMMA=0.35 PHI=0.76 CJ=0.31e-3
+CJSW=0.17e-9 CGSO=0.19e-9 CGDO=0.19e-9 CGBO=0.3e-9 NSUB=1.9e16 NFS=1e10 TOX=200e-10
+XJ=0.14e-6 UCRIT=1.5e4 UEXP=0.077 DELTA=2 KF=4e-13 AF=1.2)
My problem is that I am not sure what exactly is the formula that computes the Idrain of the MOS.
Of course we know that in saturation
ID=k*(W/L)*(VGS-Vth)^2, where k=K/(1+
OrCAD Library file
in Spice Simulation - PCB design
Posted
I guess that you should find the full edition and take aditionally library files from there. If you are still interested, send me an e-mail or pm and maybe I can send you some libraries to try if it works.