Alex Tsekenis

I was afraid this would come up any moment now. Sure, but I would like to have the digital front-end as a retrofit. We could give different SW versions for different trafos. Try adding some real-life ESR to C7. I noticed you have eliminated the pot. divider for the current threshold reference. Are we going to adjust the current threshold with the dif amp now? I know you run out of voltage. Maybe you could decrease the gain of the dif amp? We can use those IGBTs from the other topic to simulate a short-circuit when we have a prototype. Could you post the latest asc. file?

Sorry, I know it is important to you. :P ;D

You can use a comparator to sense when the voltage has exceeded say 3.2V, and then the output from that will drive a relay, possibly via a transistor. Have a look here http://home.cogeco.ca/~rpaisley4/Comparators.html Let us know if you need help designing it.

If I haven't missed anything, your schematic will have the same outcome. You are also using full-wave all the time. Your schematic is using one diode less, but is using a changeover relay which might have speed implications; during the switchover there will be no power delivered to the tank capacitor and you will see that at the output. I also think that the sudden increase in voltage (as opposed to the smoother increase as the MOSFET's gate charges will cause a current spike which will lower the transofrmer's voltage. Maybe these factors will become crtitical if your output is set for around 12V. To do that with FETs you will need at least one more FET. The FET method will consume less power and maybe be a bit cheaper. Overall, I think this is a case of doing the same thing in a similar way using different components.

Thanks PICMaster. I can't believe they used an R2R ladder for a DAC when they had an MCU with PWM... ::)

I have never built it either. Can yu point us top any reviews? One MOSFET M1 to switch in the bridge rectifier if a high output volatge is required thus effectively adding both secondary coil voltages. When M1 is OFF, only one winding is offering power through D5 at any time. Although I haven't looked at exact numbers, since M1 is used as a switch, it will either excibit a high resistance or a very low resistance. In both cases, the dissipated power will be low. But in the case of M2 M3, they are used as the 'pass-element' and have their resistance altered in a way that the output voltage is regulated. These FETs can dissipate significant power because of that (linear regulator action, like an LM317) hence two have been used to share the dissipated power. There are factors that determine how warm the FETs will get, such as cooling or if they are the actual discharge element. In your charger it is possible that a huge resistor is used to dissipate the heat.

Here is a hard question: What magnitude of current is expected under 5 Volts across your goo?

Please could you attach your circuit diagrams to the post instead of a hosting site? You can do this by clicking on 'additional options'.

Come on Hero, if you don't stop posting I will never go to bed and it is GMT+2 here :o Besides, I am supposed to be away for Christmas. ::) Maybe it is worth adding a capacitor in series with the gate of M2, M3. This will waste some gate turn-on volatge (depending on capacitance ratios) but will decrease the gate capacitance that U1/U3 see. Maybe we can select logic-level FETs for M2/M3. I have ticked 'hide from public' in my account, does public include registered members? Yes so I run the simulation with ideal sources and ones with 0.4Ohm impedance and the difference is huge. That is what I meant by heavy dependance. With the percentages I meant what is the maximum tolerable peak-peak AC ripple as a percentage of the average DC output. If I had to choose between more coil (higher volatge trafo) and thicker coil (higher current trafo) I would choose thicker coil as it will keep efficiency high, maintain tight regulation and not fry the op-amps (assume a primary voltage spike) at light loads.

I remembered this: http://www.elektor.com/magazines/2001/november/digital-benchtop-power-supply-(1).54823.lynkx http://www.elektor.com/magazines/2001/december/digital-bechtop-power-supply-(2).54867.lynkx I have both articles, maybe we can pull some ideas or tips. Let me know if interested.

5A it is then. I have obviously looked on Google and IRF.The closest matches are the IRLR3915PBF from IRF, which comes in a D-pak and the IRLU3915PBF which comes in an I-pak. Where did you get the TO-220 pack? Meh, I am sure we will find a candidate. I agree, power dissipation is the limiting factor in this application. 37.4

I agree with PICmaster that most projects stay below 12V or so, but the higher the output voltage range, the better. That said, I do realise that with a clean design like this, increasing the output voltage is quickly limited by factors such as op-amp supplies. This design must remain clean to be attractive and cost-effective therefore more than one PSUs can be connected in series. However, as they are regulated, connecting them in parallel will cause problems so we should try to squeeze as much current as possible, without having an array of MOSFETs or a brick of a transformer. In my opinion 3A is on the low-side. 5A would be nice, 8A would be excellent, 10A and you have an outstanding PSU, capable of powering most projects (eg an audio ampilfier). Hero, I was not able to find the MOSFETs on the IRF website, they are not real parts, are they? I would prefer using a tad more expensive MOSFETs with lower RdsON than using more MOSFETs to keep it compact. Regarding gate current, a driver IC can be used (non standard?) or maybe an op-amp connected as a buffer. But then you need an extra device on the PCB as you already have 4 op-amps. Nop. :( I think 10% regulation is quite high for a power supply where a constant voltage source is important. Anyway, I calculated the no-load RMS output voltage as 13.3V for a 12V transformer rated at 3A with 10% regulation. Assuming sine wave, that is 18.86V peak, not quite sure where the 0.2V discrepancy is coming from, maybe rounding error? We both used a calculator for sqrt(2) so 0.2V is quite high. One thing to bear in mind here, is that the regulation will change as the power factor from the rectifiers changes, you are switching between half and full bridge rectification. (13.3VRMS-12VRMS)/3A=0.43 Ohms, so the secondary impedance calculation is right, you didn't over-estimate it. What I realise is that I used the word impedance and not resistance. The secondary will also have inductance that, unlike it's resistance, will not waste energy as heat but send it back to C1. I am not sure as to what range of secondary inductance such a transformer will have. So what I did is assume that the secondary inductance exhibits an inductive reactance that is equal to the secondary resistance and therefore equal to Zsec / sqrt(2) = 0.43 / sqrt(2) = 0.3 Ohm The inductive reactance of an inductor is |Z| = ω L [Ohms]. Plugging 50Hz and 0.3 Ohm into that and rearranging, I got an inductance of 9.67 E-4, i.e 967 μH. So, Hero, try simulating the transformer with two 18.8V peak sine sources each with an inductor of 967uH in series with a resistor of 0.3 Ohm. Sorry I can't help with simulation my LTSpice has a will of its own. I once again say that 10% is rather high. With such high(bad) regulation you can improve performance by increasing the output voltage of the trafo and 'sacrifice' it under load. But you will have housekeeping PSU problems when under light load. Otherwise, you can maybe increase the current rating thus decreasing secondary impedance and improving regulation? You could sacrifice efficiency by using only the full bridge rectifier to drastically reduce the peak rectifier current. But I quite like that topology, and considering all of the above I think a higher current trafo is needed. To clear your mind from phazors, I think we must concentrate on the analogue part which is what will define the performance of the whole PSU. Digipots, LCDs, DACs, ADCs are there and will allow a digital front end but will not affect things like closed-loop stability and output ripple, which are what the load will care about. Hero, could you zip and email me your lib folder and its subfolders and files?

How much current can you draw without a total redesign of the topology? By upgrading all components in the main current path we can easily get >5A. This will be very useful. 10A would be ideal. I think you meant Vout = Vref*5.1 + Vref = 6.1*Vref = 30.5V I was thinking of digipots as a retrofit but DACs will probably be cheaper. I have noticed you changed all op-amp supplies to +V+6V. Are you considering using a quad op-amp to keep the pcb compact? I still get the SPICE error. Not sure what is wrong.

I should also say that for circuit analysis (ac and dc) using passive components an excellent book is this: http://www.amazon.co.uk/Introductory-Circuit-Analysis-Robert-Boylestad/dp/0131988263/ref=sr_1_1?ie=UTF8&s=books&qid=1262006087&sr=8-1

I have associated all the file names and all the symbols load correctly. However I get the following error. See attached. Any ideas? Could you post your universalopamp.sub file?

Right, I will give them a try. In the meanwhile, what are the output specs of the project? 0-30V 0-3A? I was thinking, since you have engaged into designinmg a new one why not juice it up a little bit, say 50V 5A? I was also thinking how nice a digital front-end would look like, a small LCD with up/down buttons to set current limit, attack time and output voltage. I am very keen on a portable powerful psu with a fancy front panel.

Ok, we need the universal op-amp asy and the sub file it points at. Also, the upside-down op-amp asy and the sub file it points at if different. Zip and attach if possible.

My main concern was latch-up of switch-mode PSU controllers when a bath-tub voltage input is applied, hence the delay. I think that the actual delay time will require experimentation in the particular application. Most circuits will not mind whatsoever, maybe a few MCU design will fail to reset. A setting could exist that applies a delay as a function of current drawn, like in an inverse time overcurrent relay. Maybe this is an overkill as the currents involved are rather small and ultimately limited by the transformer. An adjustable 0-100ms adjustable rise time on the output of the current sensing dif. amp should be enough for most applications. I expect the output resistance to be too low to allow for a reasonably small capacitor, but you can subtract it from the resistor value (tolerances?) There is a compromise here, how much time your tank caps take to charge and how much time an IC or transistor at 3A takes to blow up. I did look at the schematic, particularly interested in topology. Would you share the LTSpice file? I can have a block-by-block look then. How does the PSU behave with a step on it's output, say 10% to 100% current and back? How about adding some resistance/capacitance to the sine sources?

A few 10s of ms I would think. How about a capacitor between the output pin of U2 and ground through a variable resistor? No further modifications needed. You can cover a huge range with a reasonably sized capacitor as you can always set R=0 with the variable resistor. Wiper debouncing will be taken care of by the capacitor following it.

You will have free electrons but you will not have current. You will need to accelerate them in an electrostatic field. The current integrator will integrate the tiny current over time, thus measuring charge. If you know the time, you can work out the number of electrons freed. The current integrator will probably take the form of an op-amp with a capacitor in the negative feedback path and a grounded non-inverting input. Your output will be -(1/C) x integral of (Iin) dt [Volts]. But you need to get those electrons moving.

I have a dual 36V, 4A PSU that can be used to simulate the transofrmer and PSU. However, we will be deviating from the idea of testing the whole prototype. Don't worry about testing, you have me willing to do it if noone else is keen, so I would tick that on your list. I would like to test the entire prototype if possible, maybe help with PCB design?

OK, 50mOhm is not tragic. I agree with standard components for this project. RC constant is the first thing that comes in mind here too. I dont think more than two settings will be needed, one slow and one very fast, so maybe a simple SPDT switch that connects a resistor in parallel will be sufficient. No, it needs testing no matter who designed and reviewed it. What I meant was, what will you need for your testing? Are you going to built it on a breadboard/perfboard and have someone else test it? Submit a schematic, someone builds it and tests it? etc. As long as people use the components in the BOM and havent messed up, it must work, and that is what we should aim for. Now, if there are some non 555-like parts, you could offer an alternative and test that config too. But you cant test every possible config. You will invest time developing the circuit around some specific parts therefore whoever builds it must invest time in finding the parts, possibly with help from us. Otherwise your efforts are in vain. Have a look on Maxim-IC, their sampling system is like Santa Claus these days.

What would you like to have tested Hero? I would like to see a setting for the attack time of the current limiter, a feature not found on cheap or DIY power supplies. 50 Ohm still sounds large to me, how about something in the 10's of milliohms range and a low input voltage offset differential amplifier? LT does such ICs, maybe it is worth having a look there.

I think he means this one: http://www.electronics-lab.com/projects/games/001/ You build the project and give it your partner, batteries included! Hopefully they will appreciate your effort and think that you love them. You can then take it from there ;)

Your toilet fits the description :P On a different note, I don't think anyone here can readily help you with the theory behind your goo without pre-reading/research. If you can synth some goo, we can help you develop a conductivity meter.