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# Flight17

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1. ## 0-30 Vdc Stabilized Power Supply

I thought it might be interesting to look at the input voltages of U2 under various conditions in my current design (iteration 18) in Multisim. I could get the NI input of U2 as low as -1.1v by setting current and voltage pots to 0.0 and reducing R17 to zero. In my current design, R17 goes to ground as the voltage ref for U3 is relative to ground (to solve the nonlinear problem and allow me to display the CL setting on the current meter). That means my sim doesn't directly relate to the rev 7 design. Plus, R17 won't be zero. Nonetheless, I see no real harm in powering U2 from the -1.3v supply instead of ground, so I think I'm going to do that. It increases the supply voltage by 1.3v closer to the 44v limit, so I may drop the upper supply to U2 by a bit with two diodes or a small zener.
2. ## 0-30 Vdc Stabilized Power Supply

Yes, I understand this. Responding to your numbered points: 1) Agreed. 2) "Voltage is set to 20.0V and current is set to 1.0A. A load of 10 ohms is applied. The output voltage must drop to 10 ohms x 1A= 10V and the output of U3 drops to about +3.13V. The input of U2 is about +3.73V." I think we agree here, too. The input of U2 has to be just low enough that the positive output is 10v, measured relative to the negative output terminal. Measured relative to ground, we add the 1A times the resistance of the R7 current sense resistor, or 10.47 volts. To get nominal 10v output, the input of U2 is down by the gain of the U2 amp stage set by the feedback resistors R12, R11, RV2. It should be around 3+ volts and the output of U3, setting the CL will be 0.6 lower, so those numbers look right. 3)" Voltage is set to 20.0V and current is set to 1.0A. The output is shorted. The output voltage must be 0V and the current must be 1A. The output of U3 drops to about -0.04V and the input of U2 is about +0.56V. The output of U3 will never go below -0.04V which does not harm it since its negative supply is -1.3V." This looks right, too. "The gain of the voltage amplifier is 30V/11.2V= 2.68 and the output of U2 never goes below about +1.2V due to the driver and output transistors Vbe voltage drops. The non-inverting input of U2 is always at least +1.2V/2.68= +0.45V when the voltage and current settings are zero and there is no load. Many ordinary opamps have inputs that do not work when they are a few volts from the negative supply pin, but the inputs of the TLE2141 work all the way down to the negative supply pin voltage." OK, put that way, assuming that both transistors are always forward biased base to emitter, I understand. But is that assumption warranted? Are there no conditions under which the input of U2 might be low enough to drive the output low enough to cut off the transistors? I can see that assuming that they aren't in cutoff requires an input that is safe, but I don't understand where that assumption comes from (not disagreeing, just haven't worked through it yet, and it was the only way to explain my simulation problem I could come up with.) "Isn't the idling current simply the 3.4mA to 4.4mA current of U2? You are correct, U2 gets hot but not too hot." The rev 7 design has the idling current of U2 going direct to ground, so the current limiting circuit doesnt see it. It's the idling current of U1 that goes through R7, so there is 3.4 to 4.4 mA for the TLE 2141. Also, there is another 5.6mA idling through zener D8 and R4. The rest comes from gain resistors on both U1 and U2 and pot P1, but its minor. Most of that is eliminated by removing U1. "The driver and output transistors need huge non-enclosed heatsinks or a fan." Yes. I even considered adding another 2n3055. (4 instead of 3). The present heatsink is roughly 7"x8". Also, my transformer has two additional 10 vac rms windings, each rated for 5A, I intend to connect them in series and provide a 20v second supply in the same housing that I will use for lower voltage high current conditions. I might even use a relay with the windings to autoswitch so that they are in series only when needed and at the lowest voltages, high current conditions, only a single 10vac rms winding is in use. That way the main supply will seldom run at low voltage high current, except when accidentally shorted Thanks for taking the time to reply. I really appreciate it.
3. ## 0-30 Vdc Stabilized Power Supply

Ok, here's my question. The D9 diode pulls down towards the -1.3v supply when current limiting is in effect. Depending on the op amp selected, the output of U3 can go as low as its negative supply (-1.3v) or 0.3 higher than that (-1.0v). The D9 drop is 0.7 volts max, so doesn't the input of U2 see a negative voltage under conditions of very low current flow through R7? IIRC, the minimum idling current in ver7 was at least 12mA, producing insufficient voltage to ensure that the NI input of U2 remains positive. The specs of the two 44v opamps require it to be either no lower than the neg supply, or no lower than 0.3v below it. Perhaps this is only a problem for my redesign, where I've reduced the idling current to below 2mA. I mention it only because one of my simulations went into what looked like phase reversal. It went to max voltage and current under conditions where output current approached zero and R17 was small. I solved that by connecting U2 to the -1.3v supply. That made it almost impossible to use anything other than a 44v opamp for U2, and there was no real benefit to a lower voltage OA anyway. Ok, that's it for now. I'm still finalizing the design, checking some things, like U2 power dissipation with almost 43 volts across it. I may need to adjust the drive circuitry. (IIRC, the TLE U2 needs 4.6mA, and Q2 needs another few mA to drive 100mA into the three 2N3055s with hfe at around 50-90. I don't recall the power dissipation rating of the TLE2141. Just checked, and the plastic pkg TLE2141 has 84.6 °C/W so figuring 4.6mA plus 3mA drive I get 7.6mA x 43v= 326mW resulting in a 28°C rise above ambient temp for Tj. If I did that right (remember I'm a beginner) it looks OK to me.
4. ## 0-30 Vdc Stabilized Power Supply

Ok, continuing on. Although I think U2 *could* be driven from a regulator, my current design doesnt do that. It uses a 44v OA, probably the TLE2141, although I haven't made a final selection. The reasons are: 1) the voltage requirements 2) the null offset pins available. 3) the PSRR pwr supply rejection ratio is quite high (98 db IIRC), as recognized in the original design, so the fact that it's powered from the unregulated supply has little effect 4) one more thing as discussed below in my question, when I get to it The comment about using the lm317 relates to U3 and U1, not U2. U3 only needs to get above the 11.2v voltage reference, and -1.3v to pull down D9 at the U2 input. So it can easily be powered by an lm317. Further, there are several reasons why I want a regulated supply. I plan to eliminate U1, the voltage reference. And replace it with two tl431 adjustable voltage references. One will be the 11.2 reference relative to the top end of the current sensing resistor R7, at the negative supply output. The other will be 2.5v relative to ground. The first of those references is used to provide the output voltage reference for U2. That reference voltage floats above the R7 current sensing resistor voltage. The second reference is used to provide the current limiting reference for U3. By using a current limiting reference that is fixed relative to ground potential, I solve the two problems discussed in my earlier post which are: 1) nonlinearity of the current limiting potentiometer and 2) the problem of the current limiting output voltage varying as the load current flowing through the current sensing resistor varies. That allows me to use the current meter to display the current limit setting. To do that, however, I need another op amp (U4). So, like the original design I end up using a 3 op amps, but two of them can be on a dual chip powered by the lm317 and operate at a much lower voltage than the 44 volt chip used for U2. The regulated output of the lm317 cooperates with the adjustable zener tl431s to give excellent voltage regulation. It also reduces the idling current through R7, so the voltage across R7 more accurately reflects the load current through the output terminals. Edit: I should have said that the lm317 regulation was helpful in providing much more accurate tl431 voltage references, as compared to driving them from the unregulated supply. It wasn't all that critical to the dual op amps.
5. ## 0-30 Vdc Stabilized Power Supply

As to the 33v lm317, I wasn't clear. Let's look at the output. From ground, we need 1.35 volts at 5A across thecurrent sense resistor R7. We need 30v across the output. We need another .5v assuming 1.6A through each 2N3055, another .6v base to emitter in the 3055s and another .6 across the base to emitter of the driver Q2. That's a minimum of 33.05v at the U2 output. However, U2 can't swing to its upper limit, so we need another 1v at least, giving us 34.05v output for an lm 317, which needs 3v headroom, giving us 37.05 at any lm317 feeding U2. ... and those are all fairly conservative numbers. I considered doing it - by using a smaller load sense resistor, I can get down to 1.0 to 1.25 v. By using the emitter resistors in the original supply (0.2R) I get 0.4v. I could use a low dropout regulator and large filter caps to get it to work. I'm still in the middle of replying, but are you saying the other 5A designs I've seen won't work? I just finished testing at 1.3v 5A output across the load resistor, which equals 0v out at the output terminals. I ran for 5 minutes. It needs active cooling on the 3055 heat sink and a large heat sink on Q2, but it looks like it will work to me. I'm slowly heading to a question and comments in my next post.
6. ## 0-30 Vdc Stabilized Power Supply

I'll try to reply. First, itried to repost the rev 7 schematic. I'm stuck using a smartphone, so it may take me a while to get it correctly posted. The rev 7 schematic is marked as 3 amps maximum. However I'm just using that schematic for reference numbers.. I've referred to many other schematics that have been posted here with 5A mods, and the changes are minor. A larger filter capacitor, a diode bridge capable of handling the increased current, a larger transformer, an additional 2N3055, and a reduction in the current sensing resistor are the primary changes. I've got an older broken 5A phone power supply with bridge rectifier, transformer, 3 2N3055s and heat sink, fusing etc. that will be the basis for the supply. I've tested it at full output (filter caps in place 30acv rms=42.4-1.4v dc out at bridge output = 41v at filter caps and 5A output with almost all of that voltage dropped across the 2N3055s) so all I need to build is the voltage and current regulation circuitry.
7. ## 0-30 Vdc Stabilized Power Supply

I agree, keeping the ref numbers unchanged is important. I've kept your numbers on all my schematics. My ver7 schematic has what you posted above for the "original schematic". It "has U3 as the current regulator, U1 as the voltage reference and U2 as the voltage regulator." P2 is the CL pot that sets that current limit. Originally, I planned to do exactly as you suggested, "simply use the circuit's 0V as the meters ground and measure the voltage across the current-setting pot for the current limit setting and measure the voltage across the current sensing resistor as the actual current of the load." But that doesn't work. The "voltage across the current sensing resistor" does work, almost. It is close to "the actual current of the load." except it includes some idle current as described above. That's not a big problem, and I can work around it. However the "voltage across the current-setting pot for the current limit setting" isn't even close to the CL setting when measured relative to 0v ground. The voltage across P2 is a percentage of 11.2v plus the voltage across the current sensing resistor R7. That's because the reference voltage 11.2v floats at that reference level above the end of the current sense resistor connected to the supply negative output (to hold the supply output voltage constant) while P2 is connected in a resistor divider arrangement between 11.2v plus the measured load current voltage and ground. Basically, the voltage on the wiper of P2, which sets the CL and is connected to the U3 NI input, changes its voltage significantly as the load current changes. It's only at the "correct" CL voltage when the load current is at that same voltage across R7. It was kind of surprising to me when I first realized that. Because of that, I can't just measure the voltage on the P2 wiper to know the CL setting. As discussed above, that has other effects. It makes the CL pot control slightly nonlinear, and I've got some numerical 10 turn pot dials I'd like to use, so I'd prefer better linearity. Example: At full current, the voltage across the load resistor is .27Rx5A=1.35 v The voltage from ground to the 11.2v ref is thus 12.55v and ignoring the small R17 below P2, P2 will have 1.35 volts across it, with the wiper at the top, and that is 10.76% of that total 12.55v. However, if the load current now drops by 50%, then the resistor divider with P2 at its bottom will only see 11.2v + .675v=11.875v and P2 still has 10.76% of that decreased voltage or 1.28v across it instead of 1.35 volts. If we measured the wiper voltage now, we'd think the CL setting had been reduced, even though the wiper is still at the top of P2 and the CL is still at 100%. When the load current actually reaches the set limit, then the P2 wiper will have 1.35v on it, but until the load current actually reaches that limit, we can't know the CL setting just from the voltage on the P2 wiper. If we now wanted to change the current limit to 50% of max output, P2's wiper would need to be set to half of 1.35v to get 50% of max CL, so P2's wiper needs to be set to 52.8% of its range not 50% since 52.8% of the 10.76% of the total 11.875v is 50% of 1.35v. IOW, setting P2 to 52.8% is needed to get the correct 50% CL. The nonlinearity problem gets worse at 25%. I know, its not much, and I'd ignore it if not for the fact that the voltage on the P2 wiper varies significantly as the load current varies. That voltage just doesn't tell us what the CL setting is.
8. ## 0-30 Vdc Stabilized Power Supply

To get the same terminology, I'm referring to the rev 7 schematic, where U3 is the current limit control and U1 is the 11.2v ref voltage and U2 is the voltage control. I understand that U3 has to go negative. That's why it's connected to the -1.3v supply. However, U1 does not need to go negative (and its V- is connected to the negative pwr supply output at R7, which is always above ground potential). U1's output is always 11.2v above the negative pwr supply output, so it doesn't need connection to the negative supply. I'm really a beginner, so don't take this as criticism of the design. It's not, but it looks to me like U1 could have V- pin4 connected to the negative output (as in the rev 7 design), to ground, or to the -1.3v supply (assuming one doesn't exceed the 44v limit). Either of those changes would cause the U1 idle current to skip the current sense resistor R7. In the rev7 design, it really doesn't matter that idle current flows through the current sense resistor. The current limit voltage at the noninverting input of U3 is only relevant when the current limit is reached, so the fact that that voltage changes (relative to ground) as the current changes isn't important. It will be correct when the P2 set current limit is reached. (I'll note, however, that it makes the current limit pot very slightly nonlinear, due to effects on the offset zero point at R17). However, I'd like to use the U3 input voltages to display the current limit setting and actual current, so I don't want the CL limit voltage to change as the current changes. I can do that by changing the reference voltage for the CL setting to be based relative to ground, while still leaving V- of U3 connected to -1.3. Further, it might be nice for 0v at the CL pin to correspond to 0mA CL setting. That's a problem since the rev 7 design has current flowing through the R7 sense resistor that isn't flowing through the load connected to the output terminals. The U1 quiescent idle current (2-4 mA, depending on the OA used) flows through R7. Also the 5.6mA used for the D8, R4 vref, the R5-R6 gain resistors around U1 (another ~0.5mA) and the P1 voltage set pot current (another ~1mA) all flow through R7 current sense. Those last 3 have to go through R7 (although they can be reduced somewhat with design mods), but it looks to me like the U1 quiescent idle current could go directly to ground and bypass R7. If I understand the circuit, the purpose of R17, below the P2 adjust pot is to counteract for those effects that cause the 0 amp CL setting to be above 0v across R7 current sense. None of this is important unless you want to use the voltage at the input pins of U3 to display the actual current and CL setting, as I do. As I said,I'm trying to learn, and one way is to try various modifications and try to understand the effects. I could just offset the voltage at my voltmeter (used to display current and CL limit) to null out the quiescent current so that the meter reads zero when the voltage across the R7 sense resistor equals the quiescent current due to those effects described above. I think I can do that by measuring relative to the voltage at the top of R17, which should equal that quiescent current times R7. But I can also just reduce those effects by making them small enough to ignore. I'm considering eliminating U1 and replacing it with a TL431 which can run at a milliamp or two. That removes the U1 quiescent current, the D8 zener current and the R5-R6 gain resistor current. Then increasing the resistance of the P1 voltage pot cuts the total current down to levels I can probably ignore. I'm playing with simulating that approach (Multisim) and with just offsetting the quiescent voltage on R7 current sense by measuring voltages relative to R17, not ground. (This may be best). I freely admit I may be off base here, but I'm learning as I go, and it's fun. I do hope others with more design experience will point out flaws in my thinking, but if they don't, and I end up building something that doesn't work, I'm happy with that, so long as I figure out what went wrong. I can always build version 2. <smile>
9. ## 0-30 Vdc Stabilized Power Supply

Another change I'm thinking about is the Vref for the current limit IC U3. I'd like to be able to press a button and have the current display show the current limit setting. The rev7 design (all the rev designs) use the same refvoltage from U1 and the 5.6v zener D8 for both current limit setting and voltage setting. However, the vref is relative to the negative output, not ground. That's required for voltage setting, but it creates problems if you want to use the + input of the current limit comparator op amp U3 to know the current limit setting. IOW, the voltage that sets the current limit changes as the current changes. I'm thinking about using a second vref for current limit control that is relative to ground, not neg out. That way, I can switch between the two inputs of U3 to display the actual current when looking at the inverting input and the current limit setting when looking at the noninverting input. It adds another component, but I've got several TL431 devices, which are cheap, so the cost is low. Another thing I'm trying to understand, is why U1 is powered between negative out (not ground) and the unregulated supply. That means that its operating current and the current supplied to the vref pass through the sense resistor R7 and are part of the current being limited. I wonder if it can be connected to ground and allow a more accurate current limit setting. I'm not saying the rev7 design is wrong. I'm very much a beginner, but I'm having fun trying to understand why certain design choices were made, and what effect other choices would have. Using an lm317 to power the op amps has the benefit of limiting the OA voltage to 36v or less, and that opens up the choices for op amps to more than the 44v only ones being used. If I go with the option to have the current meter display the CL setting, I need another OA with high input impedance to prevent loading the CL limit input of U3. That has the added benefit of letting me adjust the gain, so the 1.3v on the current sensing resistor R7 at full current will display 5.0v=> 5.0amps and I can use one of those cheap low impedance ebay high accuracy voltmeters for current display without modifying it. (They have 350k input impedance). I'll also have multiple choices for 36v dual OAs that are cheap. I'm thinking of a dual OA for CL comparator and current/CL display and something that is either very low Vio or with nulling inputs for the voltage comparator OA U2. I'm playing with design, and simulation software and having fun. It's better than staring at the ceiling in a hospital bed. Comments are always welcome, but, truly, I'm a beginner, so don't take any of this as criticisms of the published designs. PS. I'm thinking of using the TL431as the vref since it has a low tempco compared to zeners I've looked at.
10. ## 0-30 Vdc Stabilized Power Supply

I'm building the Rev7 0-30v 5A design, but I'm modifying it as I go. I'm disabled and bedridden, so I can only work on it for short periods, but I can think about it for long periods :-) I'm trying to learn as I go, and I've chosen this project as my learning platform. I look at the various design choices and options, and the different changes made by others, and try to understand the effects of each change, then try to choose modifications based on what is cheap and what I've already got in stock (scavenged parts). I'd like to ask a lot of questions, but I hesitate to bother people here, so I try to work out the answers myself. I don't want to imply that the published design is less than optimal, when what I'm really interested in is learning and trying to understand what options there are.Here's an example. I'm going to use an lm317 to hold 33v instead of the D13 zener. It lets me widen the range of usable op amps.
11. ## 0-30 Vdc Stabilized Power Supply

Thanks for the reply. I was looking at several generic charts of zener tempcos, not realizing they varied that much. I had a few 5.6v zeners and tested them (just used mild hot air and watched the voltage change), and all seemed to have significant positive tempcos at 5.6mA. Adding a series diode with negative tempco helped a lot. I located a BZX79C5V6RL datasheet and see why you chose it. I see that it is marked at -2 to +2.5 mV/C at 5mA, so I guess mine are in that range, as they seem close to +2. Since I've already roughly tested them, I might as well use the series diode.
12. ## 0-30 Vdc Stabilized Power Supply

I've a couple of questions. Although the MC34071 isn't available any more in through hole packaging, the MC33072APG is (same or better specs than the MC34071). Although there aren't any offset null pins in this dual OA package, is there any reason not to use it for U1 and U3? It's cheaper than the TLE 2141 (\$0.53 per amp compared to \$1.86 for the TLE) and it runs cooler. The TLE will be used for U2 where offset null is needed. The writeup describes the 5.6v zener as being operated at its zero tempco current, but my research shows that the zero tempco current is closer to 0.01 mA than 5.6 mA where it runs in this design. At 5-6 mA, the tempco for a 5.6v zener is about 2 mv/C, which is about equal to and opposite to the tempco of a Si diode. That's why you often find 5.6v zeners in series with a Si diode when used as a vref. Is there any reason not to add a Si diode in series with D8 and adjust R5 R6 to get the 11.2 voltage reference? It seems to me that would improve performance at almost no cost. Thanks for any comments.
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