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# pulse width modulation

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Pulse width modulation involves a capacitor and associated logic. When logic is applied, the capacitor is allowed to charge at one rate. When logic is applied, the capacitor is allowed to discharge at one rate. I suppose you could use a 555 timer, but isn't there an even simpler circuit if someone could post it.

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Kevin,

This is as simple as it gets I think.

Ante ::)

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Kevin,

The circuit have a fixed frequency and a variable pulswidth from 0 to 100%.

Ante ::)

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Kevin,

I don

and here:

and another:

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Can anybody see the problem with analyzing this circuit. There is a peculiarity that exists. The first ciruit. What makes the output of the first inverter go low when it's high?

I think it may be the high to low transition of the second inverter. This means the low has to go through D1 and the resistor. Which is okay, but doesn't the resistor value need to be on the low end.

I have seen another peculiarity in another oscillator circuit. The transistion causes the input to change opposite of the transition because the capacitor passes the signal caused by the transition.

Isn

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I think I understand the operation of the circuit with one inverter. But why use two inverters. The last circuit only uses one inverter. The operation with two inverters doesn't make sense because the output of the second inverter would tend to stay high. Could somebody explain why one or two inverters can be used. I have seen two inverters used before, but the operation is a little different.

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Kevin,
The last circuit uses a Schmitt trigger inverter as an oscillator. Like the other circuits, its duty-cycle is varied with the diodes and pot, to perform PWM.
The other circuits use 2 inverters in a classic CMOS oscillator.

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When the output of the second inverter is high, it will charge the capacitor high, which sends the output low. You have the discharge of the capacitor which allows the ouput of the second inverter to go high.

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Kevin,
You have questioned the operation of a classic CMOS oscillator many times before, so I would like to explain its operation to you:

A) The 2 CMOS inverters have an input threshold voltage of mid-supply. If a CMOS gate is used as an inverter, only one input should be used to keep the threshold at mid-supply. With an input voltage below the threshold, the inverter's output is high. Likewise, with an input voltage above the threshold, the output is low.
B) When you apply power to the circuit, the capacitor is discharged, so has 0V across it. Since the inverters are connected in a circle, they have positive feedback, so that one inverter's output is high and the other's is low, and will remain in whichever state that they power-up in, until the RC network changes it. So if the output of the 2nd inverter is high, then it connects through the discharged cap to make the input of the 1st inverter also high. Therefore the 1st inverter's output is low, which is connected to the 2nd inverter's input, which continues to make its output high.

Here is how they oscillate:
1) Assume that the output of the 2nd inverter is high, as in B above. The capacitor charges through the diode-resistor from the low voltage at the output of the 1st inverter.
2) The voltage at the input of the 1st inverter (which started high) follows the voltage of the charging cap and drops to its threshold voltage.
3) When the threshold voltage is reached at the input of the 1st inverter, it begins to change state, and since it has a lot of gain, its output quickly rises to the threshold voltage of the input of the 2nd inverter.
4) The input voltage of the 2nd inverter started low, but now that the voltage has reached its threshold, then its output begins to drop.
5) The dropping voltage at the output of the 2nd inverter couples through the cap to the input of the 1st inverter.
6) The input voltage of the 1st inverter, which was dropping anyway (#2 above) continues to drop and the high gain positive feedback-connected inverters' outputs "snap" quickly to the opposite state.
7) Now the cap discharges through the other diode-resistor until its voltage reaches the threshold voltage of the input of the 1st inverter, and the positive feedback-connected inverters' outputs "snap" quickly to the opposite state again.

The pot adjusts the charging resistance for the capacitor. The diodes allow the cap to charge/discharge only one way through its part of the pot, so that if the pot is set near one end, then the cap charges quickly and discharges slower, resulting in the inverters' outputs having an adjusted duty-cycle which is called PWM.

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I think I can corroborate. Let's start with what we can easily agree upon. The output of the second inverter goes through the capacitor. This is the first observation. The capacitor will charge to 5 volts, bringing the high that went through the capacitor to 0 volts. Are these two observations correct?

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Kevin,
1) Sort of. I wouldn't say that the high output of the 2nd inverter GOES THROUGH the cap (but I know what you mean). I would say that since the cap is discharged and has 0V across it, and since it is connected to the output of the 2nd inverter, then its other end that is connected to the input of the 1st inverter is also high.
2) Correct. The capacitor will charge through the diode and resistor, since the resistor is low by the output of the 1st inverter.
But it will not charge to 5V, but actually down to only mid-supply (2.5V), since that is the threshold voltage of the input of the 1st inverter (which was high), and at that point the inverters switch states.

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I will have to disagree with you about the thresholds. I don't think they are necessary in deciphering the operation of the circuit. But I will continue to read your posting to determine otherwise.

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Kevin,
The fact that the input voltage threshold of a CMOS inverter is at half-supply is very important to the operation of the classic CMOS 2-inverter oscillator, and is also important for its use in PWM. The threshold is at half-supply because the N-channel and P-channel MOSFETs are manufactured to be very symmetrical.

Attached is the datasheet of Fairchild's CD4069 CMOS Inverter.
On page 4, the 1st graph,"Gate Transfer Characteristics" shows that when the inverter's input voltage is near half-supply, then a small change in the input voltage causes a large change in the output voltage, and the positive and negative transitions are very symmetrical.
The datasheet is here:

Cd4069ub.pdf

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• 1 month later...

I have since found that a third inverter added to the classic oscillator makes for a much better square wave. MP said that a two inverter oscillator migh have trouble starting up. But I found the third inverter to make the square wave better and the startup was never a problem. The output of a two inverter is really bad.

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Kevin,
If the output of your 2-inverter oscillator is bad, then perhaps you are not using a series resistor that has a high enough value (10K minimum).
Also, maybe your output is from the wrong inverter.

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The circuit is correct. The problem is that the classic oscillator has a capacitor charge discharge to it. This makes the square wave not so square.

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The CMOS inverters in a 2-inverter oscillator have a voltage gain of about 100 each. Therefore the charge/discharge of the capacitor is amplified 10,000 times, plus the circuit has positive feedback to speedup the switching even more. The outputs of all the 2-inverter oscillators that I have built and seen are very good and fast square waves.
If the output is taken from the 1st inverter that has the capacitor in series with its input, or if its series resistor or the other resistor is too low in value, then the square wave will have rounded corners.
I agree that adding an inverter to the output of a 2-inverter oscillator makes the square wave even better.

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