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DIO Protection


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Greetings,

I have a design question at hand:

I have a group of DIO lines, attached to an FPGA, running +3.3V signal levels. Obviously I would like to drive the signals with buffers, which is simple enough. The problem is the outside world of this device has the probability of pulling the DIO lines up to +28V (this would be an accident, not a common occurance). I've been searching for SMT or BGA solutions to this problem (ie. a buffer with this much protection on the output side) and have found none. If, by chance, anyone knows of any ICs that are capable of such a feat, I would greatly appreciate it. In the event no one knows of any individual ICs that would accomplish this task, a discrete component solution will have to do. If anyone has any recommendations, perhaps even an example schematic, it would be appreciated (using Zeners, resistor networks, etc.)

thanks for any help!

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  • 3 weeks later...

By resistor and zener you mean:

DIO ---/\/\/--------- DIO OUT
|
----
/ \
|
|
GND

I choose a zener with zener voltage equal to the DIO voltage level .. but what about the resistor ... isn't the resistor going to cause a voltage drop? what is an ideal value for a 3.3V level ?

Thanks for the help!

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The MOV might be the best choice since you are only using 3 volts. Yes, you will have a voltage drop across the resistor. You must always have a larger input than the zener voltage to make this workable. Your voltage drop will be the value of Vinput - Vzener. This voltage drop divided by the resistor value will determine the current of your circuit.

MP

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Ante,

My setup requires the protection to be "resetable" .. as in not a fuse blown but just protection that won't stop the system from running. Also, is this setup applicable to a DIO line? The circuit shown is for a power supply...

(my thanks to everyone who has been replying!!)

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  • 1 month later...

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