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shiva garg

Set up time and Hold time

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Hi Shiva,
The set up and hold requirements stem from the fact that if 2 logic signals change simultenously at the input of a digital sequential circuit there is a possiblity of metastability.Which physical phenomenon is responsible for that I still don't know,if anybody on the forum knows,I will be glad to understand.

But,what is metastability?A metastable state is a stable state between logic 1 and logic 0.A digital sequential circuit has not 2 but 3 stable states where it can reside for indefinite time.So if circuit resides in this metastable state i.e between 1 & 0,for eternity,the further logic computation will hamper.Both Q and nQ o/p's of a flipflop assume same value which dose'nt correspond to valid 1 or valid 0.

Theorotically a circuit resides in this state for eternity,practically,due to noise,which adds to say,Q output of a flip flop and subtracts from nQ output or vice versa,and due to positive feedback,circuit comes out of metastable state and Q assumes a logic 1 and nQ assumes a logic 0 or vice versa.

mathematically,the equation for a stable state is satisfied at logic 1,logic 0 and at a voltage midway between 1 & 0.
So to avoid metastability,one input is allowd to change first and second later,giving rise to set up and hold times.These have to be kept to minimum to increase speed,so datasheets specify a min value for both.

more inputs from other members of the forum welcomed.
Shekhar



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Thanks for reply........i have read that max frequency of sequential ckt. depends upon on set up time not on hold time....is there any condition in which max frequency depends upon both on set up time and hold time...what is this condition and what will be frequency in that case.

My second query is what is race around condition ....

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