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Single-ended CMOS Cascode OpAmp Design


nickagian
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Can anybody help me with the following circuit? As you can see it is about a CMOS OpAmp, with cascode input stage. I want to find a way to bias M3,M4 (Vb) but until now I cannot manage it. Can anybody suggest me a solution for biasing and how to calculate it (I mean the W/L ratio of the MOSFETs used, considering that I want a current of 1.5mA on both M1 and M2 tails and a bias voltage Vb of about 2V).

post-15243-14279143033465_thumb.jpg

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