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The 74193 is a 4-bit counter  so it can only count to 15. But you can cascade two of these by feeding the CARRY and BORROW outputs from the first unit into the COUNT UP and COUNT DOWN inputs of the second unit., and then make some kind of circuit that feeds clock-pulses to the first (least significant) unit's COUNT UP or COUNT DOWN inputs, depending on the position of your switch. The 74193 counts on L-H transitions on one of these inputs, while the other input should be at H.

Then what is to happen when it has reached 59? Two 74193s will go on until 255 (all outputs H) and then continue from 0 again, unless some logic looks at the output lines and stop the count-up signal when it is at 59. (Obviously, it should still be able to count down from 59). Similarly, the count-down may have be blocked when the counter is at 0 (all outputs L).

This all depends on what exactly the circuit is supposed to do besides counting up and down.


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You might have to look at the data sheets for the parts and simulate what is actually in the individual chip packages for FPGA programming in this development package. I am not familiar with it. Perhaps another member of the forum also uses this package. You might also try a post in the programming forum.


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