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Could some one please explain to me how a DRL...? Wait! one more thing!


bobleny
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Could some one please explain to me how a DRL AND gate works? I looked it up online, but I just don't get it...

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/diodgate.html
http://hagar.up.ac.za/catts/learner/andria/tme880dice3gates.html
http://www.play-hookey.com/digital/experiments/dl_and2.html

Would the output always be high!? Thats what I don't get...
I also never understood why the inputs are on the cathode of the diode unless the input is supposed to be ground. In that case, what if you want the input to be a positive voltage?

Please Help!

Thanks!

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The first link you posted is WRONG! No wonder you are confused.
The second and third links have the diode Resistor AND gate correct.

If both inputs are high then the output is high because the resistor pulls the output high..
If one or two inputs are low then a diode or two will conduct and the output is +0.7V if the input is 0V.
A Cmos gate's input connected to the output of this diode-resistor gate will work fine because it needs 3V or less for a logic low if it has a 10V supply. An old TTL gate will be on the edge of working or not because it needs +0.8V or less for a logic low.

post-1706-14279143218853_thumb.png

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Hmmm... How do you make the low output, lower? Say..., 0 volts?

Also, what I don't understand in detail ( lol ):

Ok, first just want to say, electrons flow from negative to positive, or cathode to anode. Also, if electrons don't have a complete path they simply won't bother leaving the battery. You, of course, already knew this....

I made an image, which I feel accurately, explains what I think would happen. Obviously, what I don't understand is why this isn't true?

drlandgate02ap0.png

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A diode has about 0.7V across it when it conducts current. In this circuit if the input voltage is 0V (ground) then the diode conducts and makes the output voltage about +0.7V. It doesn't need to be 0V at the output because a Cmos input connected to it works fine with a +0.7V input as a logic low.

Never mind the electrons flowing. Your sketch has half the switches missing because they never make an input voltage low. If an input voltage doesn't go low then the output won't go low.
Never mind your light bulb because it shorts the output to ground. Use an LED to turn on when both inputs are high, and to turn off when an input or both is low. You can't drive a Cmos gate's input if an LED is there.
Think of the output voltage as being either high or low.

When the cathode of a diode is connected to 0V and its anode has a resistor to a positive voltage, then the diode conducts with about 0.7V across it. Then the output voltage is about +0.7V which is is logic low.
When no diode conducts then the resistor makes the output voltage logic high.

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A DRL gate is used only for Cmos logic. Its low voltage of +0.7V is too close to the +0.8V max that is allowed by old TTL logic. Nothing needs exactly 0V for an input because some extra voltage is allowed for noise immunity.
The low voltage would be about +0.3V if Schottky diodes are used.

Since a Cmos input doesn't have any current then the resistor in a DRL gate should be a fairly high value so its current doesn't load down a Cmos output that is its input.
You used a 470 ohm resistor in one of your sketches. Then its current from a 5V supply is 4.3V/470= 9.1mA. A Cmos gate's output can't supply that much current so the logic low input voltage won't be +0.7V, it might be +3V.  Then the DRL gate's output would be +3.7V as a logic low to the next input which is really a logic high voltage. 

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There where actual incidents last year where I needed to run LEDs from some OR and AND gates. Because LEDs run off of such a low current, the current running out of the "low" DRL gates was enough to turn them on.

DRL isn't the only option for making these gates. It was the most appealing because it was fast to build, not that I understood what I built... TTL was a big turn off because I don't know much about transistors and I defenently don't want to deal with multi emitter transistors...

So, Is there a way to run LEDs properly from a DRL gates?

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A DRL gate is designed to feed only the zero-current input of a Cmos input. It doesn't have enough current to power an LED and to make a proper logic low or logic high voltage.

You showed an LED connected to the output of a DRL to indicate if the output is a logic low or a logic high. I said, "You can't drive a Cmos gate's input if an LED is there." because the high voltage is the LED's voltage which is only +1.8V for a red LED. It is much too low to be a logic high.

Use a 4050 buffer or a 4081 AND gate as a buffer to drive an LED so that the output of the DRL isn't loaded down by an LED. You could even use a 4069 inverter or an inverting gate to drive an LED inverted.

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The gates in an IC, such as the 4081, have a logic "low" of 0 volts, do they not?

If this is the case, and a CMOS chip is nothing more than discrete components etched into a silicon chip, then what are the components in there?

Also, if you look at reply #6 you will see a working drawing of a DRL AND gate. Problem is, it is mechanically operated. How do I use the output of a CMOS chip to control the DRL gate? Only way I can think of is to use a reed relay, but thats just stupid...

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Yes and No.
The CD4081 is made with complimentary Mosfets, not ordinary NPN transistors and diodes like the older logic families. Their logic family is called Cmos:
1) Cmos has no input current. Old TTL had massive input current. The other old families also had high input current.
2) Cmos operates from a supply voltage from 3V to 18V. Hi-Speed Cmos (74HCxx) operates from 2.0V to 6.0V. Old TTL operated only from 5V.
3) A Cmos output goes up to the supply voltage for a high and down to 0V for a low, if its load doen't have current. Old TTL had an output that went to about +2.5V for a high and down to +0.4V max for a low.
4) The max input voltage for a logic low with a 5V supply is +1.5V for Cmos. For old TTL it was +0.8V.
5) The minimum input voltage for a logic high with a 5V supply is +3.5V for Cmos. For old TTL it was +2.0V.

As you can see above, a TTL output doesn't go high enough for a Cmos input so a pullup resistor needs to be added. Not shown above is the low amount of drive current from the output of a Cmos that isn't high enough to drive the input of a TTL to a logic low.

When a Cmos output feeds another Cmos input, there is an extra 1.5V available that provides noise immunity. Since the inputs don't have current then the output that is driving them goes up to the supply voltage and down to 0V, 1.5V past their minimum threshold voltage limit. The CRL gate uses up only 0.7V of that 1.5V leaving a noise immunity voltage of 0.8V still available.

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Hi Bob,
Your DRL gate in reply #6 has a very low value for its resistor that needs way more current than a Cmos output can provide with a 5V supply.

I looked at a Cmos datasheet and saw that its max logic low output voltage is 0.4V when it has a load current of 0.5mA. So the output voltage of the DRL gate will be 1.1V and the new reasonable resistor value is (5.0V-1.1V)/0.5mA= 7.8k. The closest higher value is 8.2k. An even higher value will give more noise immunity but it will operate slower.

The output of this DRL gate will be 1.1V or less. The max logic low voltage for a Cmos input connected to it is 1.5V so it will work fine.

post-1706-14279143219317_thumb.png

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