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KSZ8795CLXCC chip problem

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KSZ8795CLXCC has four 10 / 100M ports (P1 / 2/3/4), one 1000M port (P5), 25M crystal oscillator, SPI configuration interface and MIIM interface are not used, 1000M P5 port is connected to FPGA, and the actual hardware After connecting the P1 and P4 ports and the P5 port only uses TXD5_0 / 1, RXD5_0 / 1 and connects to the FPGA, then ask the microchip if there is a problem:
1: The external data will be directly sent to P5 after receiving P1 / 4, right? vice versa?
2: How does the P5 port TXD5_0 / 1, RXD5_0 / 1 receive the FPGA to identify whether the data comes from P1 or P4?
3: The network data from FPGA is sent to port P5 through TXD5_0 / 1 and RXD5_0 / 1. Then how does KSZ8795CLXCC know which data to hand to P1 and which data to P4?

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