Sandman101
- Jun 14, 2004
- 7
- Joined
- Jun 14, 2004
- Messages
- 7
Greetings,
I have a design question at hand:
I have a group of DIO lines, attached to an FPGA, running +3.3V signal levels. Obviously I would like to drive the signals with buffers, which is simple enough. The problem is the outside world of this device has the probability of pulling the DIO lines up to +28V (this would be an accident, not a common occurance). I've been searching for SMT or BGA solutions to this problem (ie. a buffer with this much protection on the output side) and have found none. If, by chance, anyone knows of any ICs that are capable of such a feat, I would greatly appreciate it. In the event no one knows of any individual ICs that would accomplish this task, a discrete component solution will have to do. If anyone has any recommendations, perhaps even an example schematic, it would be appreciated (using Zeners, resistor networks, etc.)
thanks for any help!
I have a design question at hand:
I have a group of DIO lines, attached to an FPGA, running +3.3V signal levels. Obviously I would like to drive the signals with buffers, which is simple enough. The problem is the outside world of this device has the probability of pulling the DIO lines up to +28V (this would be an accident, not a common occurance). I've been searching for SMT or BGA solutions to this problem (ie. a buffer with this much protection on the output side) and have found none. If, by chance, anyone knows of any ICs that are capable of such a feat, I would greatly appreciate it. In the event no one knows of any individual ICs that would accomplish this task, a discrete component solution will have to do. If anyone has any recommendations, perhaps even an example schematic, it would be appreciated (using Zeners, resistor networks, etc.)
thanks for any help!