I spotted a couple of bugs in this Verilog adder. The first occurs in the assignment of cg1[11] and cp1[[1], which I patched as follows:
if (FIX) begin
assign cg1[11] = (p[11] & g[10]) | g[11];
assign cp1[11] = p[11] & p[10];
end else begin
// original code...