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  1. R

    GDDR5 addressing

    I couldn't find this information anywhere so in case someone else needs it linking to where is was answered very nicely! If that's in appropriate maybe the moderators can delete this whole thread. http://www.tomshardware.com/answers/id-2194505/gddr5-memory-addressing.html In brief GDDR5...
  2. R

    GDDR5 addressing

    Sorry about the typo (bad example): There are 16 banks in all configurations larger than 512, 8 in the 512. Re-posting because there's no obvious forum in which to ask this and I'm not expecting the same selection of people to follow all 3 forums. JEDEC standard is behind a registration login...
  3. R

    GDDR5 addressing

    Hi, I'm trying to develop a GDDR5 controller and am slightly confused regarding the JDEC spec document - the different memory configuration possibilities all seem to be short three address bits to attain the capacity specified...? For example 512M memory, 32x mode, with 16 banks: Row address...
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