CUPL language tricks

[Dan Charette]

Hi all...

I'm trying to implement a set of latches with readback capability into
an Atmel CLPD, an ATF1504. I'm using their Prochip software and the
Protel schematic entry with it to drawup and compile the design. I'm
having a problem that I can't seem to figure out how to deal with. It
has to do with the actual programming language functions.
What I have in a simple test circuit is a single data line coming in
to two seperate D flip flops. These each have their own gate signal
and both of them share a read/write signal and an output enable
signal. Each gate has it's own output pin. Summerized pins:
Data in
R/W
OE
Gate1
Gate2
Output1
Output2
Now, the outputs of each of the flip flops run through an enableable
output buffer and the outputs of these two buffers tie back onto the
Data line. There is decoding logic to turn these on based on the
condition of R/W and the Gate 1 and 2 signals. The problem is this.
Whenever the software compiles this design, I get a compilation error
as follows:
"The variable (either an intermediate or output variable) was
previously assigned an expression. Use APPEND to make multiple
expression assignments for the same variable."
Now, I've tried using the APPEND statement and all this does is ORs
the two output buffers together which is not what I want. This design
is perfectly viable in discrete logic but getting this programmed is
another story. Does anyone have any ideas or tricks that I may be
able to use in the CUPL language that would allow me to tell the
compiler that these two output buffers do tie to the same data bus,
but only when their respective enable lines are engaged?
Thanks for any help.
Dan Charette {[email protected]}
Remove the "FUZZ"
from my e-mail address
to contact me.

"I may not always be right, but I'm never wrong."

 

[Tony Roe]

Hi all...

I'm trying to implement a set of latches with readback capability into
an Atmel CLPD, an ATF1504. I'm using their Prochip software and the
Protel schematic entry with it to drawup and compile the design....

Sorry - can't help you with your problem, but maybe you can point me to a
solution to mine?

I'm trying to decide on the way to develop a small tightly packed CPLD. I have
Protel 98, 99 and DXP, and I bought / downloaded the Xilinx CPLD stuff, and have
figured out how to do most (but not all) of the job in ABEL. But I still needed
some help, and the local Xilinx distributor (who's quite tech-savvy) suggested
nobody was using ABEL - most were using Verilog or VHDL, from schematic entry.
Trouble is I don't know how to represent what I want to do in schematic form. So
can you or anyone else give me a leg up? eg...

What are the pros/cons of ABEL, CUPL, Verilog, VHDL (in both text and schematic
source forms)? Is Protel a viable way to develop this code? And if so, what are
the tricks, and what else to I need? Or is there something better? Who has the
best docs (especially if schematic entry is the way to go)?

Regards,
Tony (remove "_" from email address to reply)

 

[Rolavine]

I recently did a design in an Atmel CPLD using CUPL. At one point I had a
problem and called ATMEL. They put me through to someone that answered right
away. This has been typical of my calling ATMEL with technical questions, and
is one of the reasons I like to design with their parts. There are some bugs in
Atmel CUPL too, and they know them very well. Try it!

 

[Paul Burke]

I'm trying to decide on the way to develop a small tightly packed
CPLD. I have
Protel 98, 99 and DXP, and I bought / downloaded the Xilinx CPLD
stuff, and have
figured out how to do most (but not all) of the job in ABEL. But I
still needed
some help, and the local Xilinx distributor (who's quite tech-savvy)
suggested
nobody was using ABEL - most were using Verilog or VHDL, from
schematic entry.
Trouble is I don't know how to represent what I want to do in
schematic form. So
can you or anyone else give me a leg up?

If you can't define it in ABEL, and you can't draw it out in schematic
form, how have you got it defined (in your head or in pseudo code perhaps)?

I personally find schematic entry limiting and clunky, and tend to use
ABEL throughout where possible. Sometimes schematic entry is the only
readily documented way of getting at special IO features, so I do a top
level schematic just for the IO, and have the whole ABEL hierarchy
packaged up in one big symbol. I prefer ABEL to VHDL for the same
reasons that I prefer C to Pascal.

As for tight packing, you may be struggling there. I still use the old
Lattics PDS for some very tightly packed PLDs on old designs.. the
compiler (Abel or VHDL) simply can't achieve the density that direct
handcrafted equation entry can. It's a bugger to maintain, though,
optimising state machines using Karnaugh maps etc. Back toi the software
analogy, this is doing it in a peculiarly obstructive assembler language.

Paul Burke

 

[Tony Roe]

Thanks Paul.

That's good advice. Sorry for the confusion. I'm sure that it can be defined in
ABEL, but I'm a novice and am struggling a little, mainly because the docs I
have seem to be more tutorials than references, and because it's hard to figure
out which features are industry-standard (which I'd prefer top learn) and which
are proprietary. But it's coming along, and with your abel-in-a-schematic
approach I might just get there.

My logic isn't all that complicated, so I don't see any problem with using
equations for most of it, especially as it seems I only need to code once for
each bit in a bus (for example), and I understand that there are ways in abel to
prevent the compiler from doing global optimization (that way if I write sets of
equations that I know will fit in one cell, they should stay there?).

What tools are easiest? Protel? Atmel? Xilinx?

If you can't define it in ABEL, and you can't draw it out in schematic
form, how have you got it defined (in your head or in pseudo code perhaps)?

I personally find schematic entry limiting and clunky, and tend to use
ABEL throughout where possible. Sometimes schematic entry is the only
readily documented way of getting at special IO features, so I do a top
level schematic just for the IO, and have the whole ABEL hierarchy
packaged up in one big symbol. I prefer ABEL to VHDL for the same
reasons that I prefer C to Pascal.

As for tight packing, you may be struggling there. I still use the old
Lattics PDS for some very tightly packed PLDs on old designs.. the
compiler (Abel or VHDL) simply can't achieve the density that direct
handcrafted equation entry can. It's a bugger to maintain, though,
optimising state machines using Karnaugh maps etc. Back toi the software
analogy, this is doing it in a peculiarly obstructive assembler language.

Paul Burke

Regards,
Tony (remove "_" from email address to reply)

 

[Paul Burke]

My logic isn't all that complicated, so I don't see any problem with using
equations for most of it, especially as it seems I only need to code
once for
each bit in a bus (for example), and I understand that there are ways
in abel to
prevent the compiler from doing global optimization (that way if I
write sets of
equations that I know will fit in one cell, they should stay there?).

What tools are easiest? Protel? Atmel? Xilinx?

Can't comment on which is easiest. All the ones I have used seem to be a
ragbag of parts written by different teams, and poorly integrated. For
example, the commonest error message with the Lattice Synario thingy is
error 0002. The error documentation starts at 1000, so I had to figure
out what this error means for myself- it seems to happen when the
schematic and the HDL don't match up in some way that isn't picked up at
compile time, but only by the fitter.

There are setting sto retain redundant logic, to prevent equation
optimisation, node collapsing etc. but they don't seem to do much in a
positive sense- as I said before, if you REALLY need to ensure that the
logic ends up in a particular GLB, the older tools, where the design
worked on the GLBs directly, seem to be the only way.

I suspect that SOMEONE knows what all these settings do, but no one
seems to have persuaded them to write it down yet in a form everyone
else can understand. Bit like GCC perhaps.

Paul Burke

 

[Tony Roe]

Thanks again Paul - I was afraid of that.

Can't comment on which is easiest. All the ones I have used seem to be a
ragbag of parts written by different teams, and poorly integrated. For
example, the commonest error message with the Lattice Synario thingy is
error 0002. The error documentation starts at 1000, so I had to figure
out what this error means for myself- it seems to happen when the
schematic and the HDL don't match up in some way that isn't picked up at
compile time, but only by the fitter.

There are setting sto retain redundant logic, to prevent equation
optimisation, node collapsing etc. but they don't seem to do much in a
positive sense- as I said before, if you REALLY need to ensure that the
logic ends up in a particular GLB, the older tools, where the design
worked on the GLBs directly, seem to be the only way.

I suspect that SOMEONE knows what all these settings do, but no one
seems to have persuaded them to write it down yet in a form everyone
else can understand. Bit like GCC perhaps.

Paul Burke

Regards,
Tony (remove "_" from email address to reply)