J
John Kent
- Jan 1, 1970
- 0
Would anyone have a circuit for the EPE TENS machine ?. Cheers .... jk
D
default
- Jan 1, 1970
- 0
I have a circuit that might be the original tens, or a very early
version - four transistors with a blocking oscillator and an audio
output transformer, used to step up voltage
from text with schematic:
The instrument uses a 14-volt NiCad battery and has a built-in trickle
charger.
The output wave is a carrier whose frequency is variable from 20 to
4,000 cycles. It is modulated by pulses with both on and off times
adjustable from 0.1 to 7 seconds. The output across 1,000 ohms - the
average body resistance between the applicator electrodes - is 15
volts.
Can post to alt.binaries.schematics.electronic if you get that group,
and want it
D
default
- Jan 1, 1970
- 0
Another one
http://www.gocs1.com/gocs1/Psionics/TENS-DEVICE.htmTHIS ZIP ARCHIVE CONTAINS DIGITALLY SCANNED JPEG FILES DETAILING THE
SCHEMATICS OF THE T.E.N.S. UNIT FEATURED IN THE AUGUST 1997 ISSUE OF
SILICON
CHIP MAGAZINE.
T
Terry Given
- Jan 1, 1970
- 0
default said:
ye gods, the layout is appalling! talk about designed to amximise EMI!
Cheers
Terry
D
default
- Jan 1, 1970
- 0
EMI? Circuit board layout? 180 milliwatt max?
T
Terry Given
- Jan 1, 1970
- 0
default said:
and how many (micro)watts does it take to fail EMI?
Its a good example of how NOT to layout a smps.
Cheers
Terry
D
default
- Jan 1, 1970
- 0
So you say,. But you offer no hard, reasoned, opinion why the layout
might radiate EMI. I doubt it would be radiating enough to be of any
concern, or even detectable unless you were looking for it with an AM
receiver placed against the TENS unit..
Microwatt's can cause problems if they are at the receiving end of a
sufficiently sensitive receiver, but they have to get there first.
This thing runs on batteries - no ground. The square wave pulses
might be rich in harmonics but it is only 200 HZ and isn't coupled
into a tuned radiator.
I think you have no idea what you are talking about. I don't buy it.
If you think it should radiate - how about some reasons why it might?
I played with Tesla coils - with a little care decoupling the 1.5 KW
supply from the power mains and a separate RF ground for the coil (to
earth under the coil - not the power ground that snakes through the
house) they barely radiate. TC running 100 KHZ with a tuned secondary
is a relatively poor radiator.
T
Terry Given
- Jan 1, 1970
- 0
default said:
microwatts can cause problems if you intend to meet any form of EMC
standard. This sort of subtlety is invariably ignored in hobbyist
publications. Try making this into a product, and see how much you waste
on EMC testing, only to be given a big black "X"
whats really important are not the harmonics of the LF square wave, but
those of the sharp edges, which are fairly quick.
The onsemi datasheet doesnt spec Tr, Tf but the oscillator frequency is
20-40kHz (25 - 50us). The switching edges will be a small fraction of
this (I havent got one handy to measure), so on the order of 1us or
less. This corresponds to a knee frequency of at least 350kHz.
not might, WILL.
look at the loop area the switch current flows in - it is huge, about
1800mm^2. It is quite simple to calculate how much noise will be
radiated from this loop (Go on, you do it, demonstrate you know what you
are talking about. If you cannot, and would like to learn, I'm happy to
show you how). Sans maths, reducing the loop area reduces the radiated
power. Whats more, there is no need to make the loop this big - even
with a single sided layout, it can EASILY be 20x smaller. Whats really
funny is it takes no longer to do a good layout than a bad one. The
difference is purely the level of understanding of whomever drew it. Oh
yeah, with Rs = 0.22R, the peak current is about 1.5A.
Likewise the secondary circuit has a very large loop, again for no
particular reason. Given that anyone who is skilled in this area (smps
design, EMC etc) doesnt do that as a matter of course, it is clear that
the "designer" is lacking skills in this area.
enough reasons for you?
how about some more: the ONLY decoupling on the smps supply is a single
100uF 16V electrolytic. This will have a good 10-15nH of ESL, so an SRF
of 130 - 160kHz. This will have bugger all effect on the HF edges, so
the primary loop area is, in effect, huge - it now encompasses the
on/off switch & wiring, as well as the batteries (which, by themselves,
add almost as much loop as is on the PCB. Its not like there isnt enough
room to place a low ESL cap (eg 100nF, short leads) right by the IC.
And of course this is NOT a decent electrolytic (if it was, it'd be
spec'd as such), so will have a LOT of ESR (I once measured a 10uF 16V
cap at 27 Ohms). So much so, in fact, that the ripple voltage across the
cap will be governed by ESR alone.
or perhaps the wirewound (AKA solenoidal inductor) used for the current
sense resistor.
disregarding EMC, look at the layout of VR2 and its 10R resistor.
Laughably poor! and designed to maximise the amount of noise picked up
by the (albeit crude) error amplifier. Whats more, it would actually
have been easier and faster to lay this out better. LOL.
I would expect crappy layouts like this from draughtsmen, who generally
know nothing about electronics but can drive cad packages. If the
"designer" did this, he should be beaten with a stick its so bad.
A decent layout would allocate the transformer pinout to place the IC as
close as possible, minimising the loop area. ditto for the secondary
circuit (although as it is a step-up converter, this is less important
as the current is lower, and H is proportional to I). Then of course use
a non-inductive resistor for the current sense resistor (eg a pair of
0R47 metal film resistors in parallel), decent electrolytics (say LXZ or
FC series caps, ESR around 100mOhms or so) paralleled with low ESL ceramics.
The input voltage is nice and low, so the LdI/dt spikes associated with
the primary loop area is probably not going to hurt the IC. re-wind the
primary and try to run it from +24Vdc, that'd be a whole nother story
now make one pass, say, CISPR22
Interestingly enough, a 300kW PWM motor drive has to meet pretty much
the same emissions levels as a toaster (whats 10dB between friends?).
Cheers
Terry
D
default
- Jan 1, 1970
- 0
So you say,. But you offer no hard, reasoned, opinion why the layout
No argument that the layout could be much better. That does look like
the work of an old DOS CAD package.
The weaknesses you mention are all legitimate. The supply should be
bypassed better, trace runs shorter, etc...
I do wonder about applying an FCC standard to a hobbyist project.
My experience is mostly practical with industrial controls - some of
which I design and build. The sites are invariably metal buildings
with metal studs in the walls. All the problems I see are power
related and about 9 out of 10 common mode, correctable with filters,
snubbers, or grounding at the point of generation. The other 10% is a
combination of brownout or line droop, and faulty connections (burned
contacts, loose connectors, worn brushes, etc..) Once in a great
while something like a piece of conduit carrying an AC magnetic field
past a sensitive instrument.
microwatts can cause problems if you intend to meet any form of EMC
standard. This sort of subtlety is invariably ignored in hobbyist
publications. Try making this into a product, and see how much you waste
on EMC testing, only to be given a big black "X"
whats really important are not the harmonics of the LF square wave, but
those of the sharp edges, which are fairly quick.
The onsemi datasheet doesnt spec Tr, Tf but the oscillator frequency is
20-40kHz (25 - 50us). The switching edges will be a small fraction of
this (I havent got one handy to measure), so on the order of 1us or
less. This corresponds to a knee frequency of at least 350kHz.
not might, WILL.
look at the loop area the switch current flows in - it is huge, about
1800mm^2. It is quite simple to calculate how much noise will be
radiated from this loop (Go on, you do it, demonstrate you know what you
are talking about. If you cannot, and would like to learn, I'm happy to
show you how). Sans maths, reducing the loop area reduces the radiated
power. Whats more, there is no need to make the loop this big - even
with a single sided layout, it can EASILY be 20x smaller. Whats really
funny is it takes no longer to do a good layout than a bad one. The
difference is purely the level of understanding of whomever drew it. Oh
yeah, with Rs = 0.22R, the peak current is about 1.5A.
Likewise the secondary circuit has a very large loop, again for no
particular reason. Given that anyone who is skilled in this area (smps
design, EMC etc) doesnt do that as a matter of course, it is clear that
the "designer" is lacking skills in this area.
enough reasons for you?
how about some more: the ONLY decoupling on the smps supply is a single
100uF 16V electrolytic. This will have a good 10-15nH of ESL, so an SRF
of 130 - 160kHz. This will have bugger all effect on the HF edges, so
the primary loop area is, in effect, huge - it now encompasses the
on/off switch & wiring, as well as the batteries (which, by themselves,
add almost as much loop as is on the PCB. Its not like there isnt enough
room to place a low ESL cap (eg 100nF, short leads) right by the IC.
And of course this is NOT a decent electrolytic (if it was, it'd be
spec'd as such), so will have a LOT of ESR (I once measured a 10uF 16V
cap at 27 Ohms). So much so, in fact, that the ripple voltage across the
cap will be governed by ESR alone.
or perhaps the wirewound (AKA solenoidal inductor) used for the current
sense resistor.
disregarding EMC, look at the layout of VR2 and its 10R resistor.
Laughably poor! and designed to maximise the amount of noise picked up
by the (albeit crude) error amplifier. Whats more, it would actually
have been easier and faster to lay this out better. LOL.
I would expect crappy layouts like this from draughtsmen, who generally
know nothing about electronics but can drive cad packages. If the
"designer" did this, he should be beaten with a stick its so bad.
A decent layout would allocate the transformer pinout to place the IC as
close as possible, minimising the loop area. ditto for the secondary
circuit (although as it is a step-up converter, this is less important
as the current is lower, and H is proportional to I). Then of course use
a non-inductive resistor for the current sense resistor (eg a pair of
0R47 metal film resistors in parallel), decent electrolytics (say LXZ or
FC series caps, ESR around 100mOhms or so) paralleled with low ESL ceramics.
The input voltage is nice and low, so the LdI/dt spikes associated with
the primary loop area is probably not going to hurt the IC. re-wind the
primary and try to run it from +24Vdc, that'd be a whole nother story
now make one pass, say, CISPR22
Interestingly enough, a 300kW PWM motor drive has to meet pretty much
the same emissions levels as a toaster (whats 10dB between friends?).
Cheers
Terry
No argument that the layout could be much better. That does look like
the work of an old DOS CAD package.
The weaknesses you mention are all legitimate. The supply should be
bypassed better, trace runs shorter, etc...
I do wonder about applying an FCC standard to a hobbyist project.
My experience is mostly practical with industrial controls - some of
which I design and build. The sites are invariably metal buildings
with metal studs in the walls. All the problems I see are power
related and about 9 out of 10 common mode, correctable with filters,
snubbers, or grounding at the point of generation. The other 10% is a
combination of brownout or line droop, and faulty connections (burned
contacts, loose connectors, worn brushes, etc..) Once in a great
while something like a piece of conduit carrying an AC magnetic field
past a sensitive instrument.
T
Terry Given
- Jan 1, 1970
- 0
default said:
its not the cad package, its the person driving it. A skilled designer
could do a far better layout on veroboard!
the three L's of layout:
Loop Area
Loop Area
Loop Area
try watching TV using an indoor aerial whilst wearing this TENS unit.
my main gripe is that its not necessary to do such a bad job, as with a
little understanding it takes no longer and costs no more to do a good job.
their approach also has the added disadvantage of teaching hobbyists
exactly what not to do.
I started out designing big AC drives, which are responsible for a large
chunk of the noise you will find in industrial situations
The trick is to confine your fields at the source.
Cheers
Terry
D
default
- Jan 1, 1970
- 0
I built the old four transistor version a very long time ago. It
caused no problems that I was aware of . . . I don't plan on building
this one.
Unless you are using the same DOS layout progy I was in 1992 or so
(same 45 degree bends by default)- it was so hard to use that small
changes required great effort - things like changing where a wire pad
go were easy enough but moving a component was more complicated than
it needed to be, and there was no provisions for changing trace width.
I could just imagine trying to meet a publishing deadline with that
drafting program - and could understand why it wouldn't be optimized.
But I don't understand why they wouldn't use tape and mylar - that
works and is easier than a poor CAD program.
True. That's where you come in.
take care
'-- '
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