ISA bus refresh

[Thierry Nouspikel]

Hello there,

I'm designing an "ISA bridge" to allow the use of PC ISA cards with an
old TI-99/4A computer. Most ISA signals are straightforward, but I have
questions regarding the PC-AT refreshing logic.

1) First, do I need to implement one? Are there any ISA cards that have
DRAM on board, but no independent refresh logic?

2) How does it work? My understanding is that the PC places successive
addresses on the low part of the address bus (SA0 through SA7 ?),
signals the REFRESH* line (active low), and pulses the MEMRD* line
(low). Presumably, memory cards detect it's a refresh and don't answer
with data, but rather refresh their DRAM no matter what the high part of
the address is. Correct?

3) If so, how many address lines should be handled by my counter?
Assuming a square row x column DRAM matrix, 8 lines would allow
refreshing of 64 Kbytes. Are there any ISA cards with more DRAM on board?

4) Timing. Several texts recommend a refresh evere 15 microseconds, but
some indicate that 31 or even 62 microseconds are ok. What's the ISA
standard? Also, what's the recommended duration of the MEMRD* pulse? Is
150 nanoseconds ok?

I also read that REFRESH* was fed OSC/18, and that OSC was usually 14.3
MHz. So that would mean 1.26 microseconds, and a 50% duty cycle(!). Is
this realistic?

5) DMA issues. I'm planning to include a couple of 82C37 DMA controllers
clocked at 12 MHz. I read somewhere that a long DMA transfer (e.g. 64
Kbytes) would compromise DRAM because refresh won't occur on time. On
the other hand, I also read that the PC-XT used DMA (chanel 0) to
refresh its memory. How is this done? Can one signal the REFRESH* line
at the same time one performs actual DMA? Should I interrupt DMA (gate
the clock to the 8237 ???) for refresh cycles?

Any help greatly appreciated.

Thierry

 

[[email protected]]

1) First, do I need to implement one? Are there any ISA cards that have
DRAM on board, but no independent refresh logic?

What cards are you trying to support? I think you will find some EMS
cards require a refresh from the host. The only other cards you're
likely to encounter that have onboard DRAM are video cards, which have
their own refresh circuitry.

 

[[email protected]]

Hello there,

I'm designing an "ISA bridge" to allow the use of PC ISA cards with an
old TI-99/4A computer. Most ISA signals are straightforward, but I have
questions regarding the PC-AT refreshing logic.

1) First, do I need to implement one? Are there any ISA cards that have
DRAM on board, but no independent refresh logic?

I think you'd be better off ignoring the refresh issue and not using
ISA memory cards. The utility of your project would be interface cards
- many people have connected them to microcontrollers.

If you need expansion memory, static ram chips from after the ISA era
are probably a better choice - simple to interface to and physically
smaller. You should be able to hang them off the same lines as your
ISA bus. While you are at it, you could add a NAND flash to use as a
small "hard disk" (use use a compact flash).

 

[Jonathan Kirwan]

Hello there,

I'm designing an "ISA bridge" to allow the use of PC ISA cards with an
old TI-99/4A computer. Most ISA signals are straightforward, but I have
questions regarding the PC-AT refreshing logic.

Solari has a couple of editions of books on the general subject. Do
you have them? One of them is called "AT Bus Design" and another is
"ISA & EISA Theory and Operation." I think. Also, Mindshare has a
book out on the topic.

1) First, do I need to implement one?

Probably not anymore. There was a time. But I believe that there are
PCs out there without ISA refresh capability or support.

Are there any ISA cards that have
DRAM on board, but no independent refresh logic?

Not only that, but there are ISA cards that can become the bus master
and, if they are, they can request a refresh cycle. Are you planning
on also generating SMEMR and SMRDC?

2) How does it work? My understanding is that the PC places successive
addresses on the low part of the address bus (SA0 through SA7 ?),
signals the REFRESH* line (active low), and pulses the MEMRD* line
(low). Presumably, memory cards detect it's a refresh and don't answer
with data, but rather refresh their DRAM no matter what the high part of
the address is. Correct?

Yes, I think it is just a somewhat simpler memory read cycle. The
address lines have to be valid before the MEMRD takes place.

3) If so, how many address lines should be handled by my counter?
Assuming a square row x column DRAM matrix, 8 lines would allow
refreshing of 64 Kbytes. Are there any ISA cards with more DRAM on board?

I had imagined that a row could encompass more than you seem to. Why
limit the column?

4) Timing. Several texts recommend a refresh evere 15 microseconds, but
some indicate that 31 or even 62 microseconds are ok. What's the ISA
standard? Also, what's the recommended duration of the MEMRD* pulse? Is
150 nanoseconds ok?

No. I think 15.6 microseconds is the absolute maximum that was
guaranteed. 15.06us was an actual figure I seem to remember.

I also read that REFRESH* was fed OSC/18, and that OSC was usually 14.3
MHz. So that would mean 1.26 microseconds, and a 50% duty cycle(!). Is
this realistic?

I'm not sure of the question. The frequency was 14.31818MHz, I think.
It was divided down for various reasons. (It was twice what the color
burst crystal often was, if memory serves, and was sometimes used by
display adapter cards.) It was bused around.

5) DMA issues. I'm planning to include a couple of 82C37 DMA controllers
clocked at 12 MHz. I read somewhere that a long DMA transfer (e.g. 64
Kbytes) would compromise DRAM because refresh won't occur on time. On
the other hand, I also read that the PC-XT used DMA (chanel 0) to
refresh its memory. How is this done? Can one signal the REFRESH* line
at the same time one performs actual DMA? Should I interrupt DMA (gate
the clock to the 8237 ???) for refresh cycles?

On the original systems, yeah -- DMA could, if long enough a transfer,
block refresh past its maximum allowed interval.

Jon

 

[Keith]

[This followup was posted to sci.electronics.design and a copy was
sent to the cited author.]

What cards are you trying to support? I think you will find some EMS
cards require a refresh from the host. The only other cards you're
likely to encounter that have onboard DRAM are video cards, which have
their own refresh circuitry.

Reading dynamic memory refreshes it. Continuous reads to
successive addresses will refresh all locations. Since frame
buffers read successively, DRAM based video cards have no need for
dedicated refresh logic. Refresh is "free". The original PC used
a DMA controller and timer channel to do successive reads, so no
"special" logic there either, though it cut into performance some.

 

[Thierry Nouspikel]

Thanks for your help, guys.

I'm gonna try and find one of the Solari books. I can't believe that the
IEEE specs (P996) are nowhere to be found on the net!

Thierry