Non-linear Crss and gate drive Z

[legg]

There are a fair number of articles warning about the effects of dVdT
induced turn-on of mosfets due to current induced in Crss. These
articles seem to be aimed at recent digital circuit novices struggling
with VRMs and are limited to fairly low voltage applications of
synchronous buck regulators.

In higher voltage circuits, where the bidirectional advantages of
active switches is attempted in hard switching, the non-linearity of
Crss seems to introduce an interesting wrinkle, as it can vary over
more than an order of magnitude, depending on the instantaneous value
of Vds present through the switching transiion.

This means that totem-pole structures with identical gate drive
circuits will have high dVdt ability when they are just turning on
with a high voltage across them, while the recently turned-off switch,
with a low voltage across it, will exhibit a Crss almost equal to it's
input gate capacity.

While the larger Crss does reduce considerably as it's drain is pulled
up to >10V by the oncoming switch, the dVdT created by the fast
on-coming switch can produce relatively massive curent flow into the
gate, easily charging Cgs to the threshold, if not suitably shunted.

While the resulting shoot-through current is admitedly of short
duration, given that the current will fall to a manageable level as
the voltages across the two devices and their Crss values become equal
in some tens of nanoseconds, the current available during this time
can be quite large. The resulting power loss can also be signifigant.

This suggests that the gate pull-down current capability of the
drivers must be some order of magnitude larger that the gate turn-on
current; that standard safety margins of 6:1, that are intended to
compensate for nonsymetrical drive amplitudes around the gate
threshold and an approximately 'linear' Crss, will be ineffective.

Has anyone else out there run into this problem when operating mosfets
at higher voltages, when the full range of Crss is experienced?
Obviously this is not a soft-switching circuit I'm talking about - but
hard switching is still a factor in many commercial circuits, under
one condition or another, even when soft switching is attempted, or as
an ancilliary to producing an assisted transition employing smaller
and faster switches outboard of the main power train.

I expect that lower voltage circuits never get the opportunity to
demonstrate this initial period of Crss imbalance, as a 15V change in
drain voltage is usually enough to enforce Crss equalization in the
totem-pole structure in a 36volt wafer process-limited system.

RL

 

[Ban]

legg wrote:
|| There are a fair number of articles warning about the effects of dVdT
|| induced turn-on of mosfets due to current induced in Crss. These
|| articles seem to be aimed at recent digital circuit novices
|| struggling with VRMs and are limited to fairly low voltage
|| applications of synchronous buck regulators.
||
|| In higher voltage circuits, where the bidirectional advantages of
|| active switches is attempted in hard switching, the non-linearity of
|| Crss seems to introduce an interesting wrinkle, as it can vary over
|| more than an order of magnitude, depending on the instantaneous value
|| of Vds present through the switching transiion.
||
|| This means that totem-pole structures with identical gate drive
|| circuits will have high dVdt ability when they are just turning on
|| with a high voltage across them, while the recently turned-off
|| switch, with a low voltage across it, will exhibit a Crss almost
|| equal to it's input gate capacity.
||

But also Ciss increases with low voltage and will be always at least double
of Crss.


|| While the larger Crss does reduce considerably as it's drain is
|| pulled up to >10V by the oncoming switch, the dVdT created by the
|| fast on-coming switch can produce relatively massive curent flow
|| into the gate, easily charging Cgs to the threshold, if not suitably
|| shunted.
||
If you switch the FET on, the resulting gate voltage will have a step form.
when the conduction starts and the switched voltage across the device drops
down, there is charge injected into the gate accordingly. when this charge
is neutralized the gate voltage rises to its static value
The observed high current doesn't come from shoot-through but is the
source/drain-charge flowing to gnd in a few ns.



|| While the resulting shoot-through current is admitedly of short
|| duration, given that the current will fall to a manageable level as
|| the voltages across the two devices and their Crss values become
|| equal in some tens of nanoseconds, the current available during this
|| time can be quite large. The resulting power loss can also be
|| signifigant.
||
|| This suggests that the gate pull-down current capability of the
|| drivers must be some order of magnitude larger that the gate turn-on
|| current; that standard safety margins of 6:1, that are intended to
|| compensate for nonsymetrical drive amplitudes around the gate
|| threshold and an approximately 'linear' Crss, will be ineffective.
||

Exactly that is the reason to put a diode(pointing away from the gate)
across the gate resistor. You will see in the data-sheets that the turn-on
time is much smaller than the turn-off time. So if you slow turn-on with a
resistor and discharge the gate through a diode, you will have
break-before-make in a bridge constallation.

|| Has anyone else out there run into this problem when operating
|| mosfets at higher voltages, when the full range of Crss is
|| experienced? Obviously this is not a soft-switching circuit I'm
|| talking about - but hard switching is still a factor in many
|| commercial circuits, under one condition or another, even when soft
|| switching is attempted, or as an ancilliary to producing an assisted
|| transition employing smaller and faster switches outboard of the
|| main power train.
||
|| I expect that lower voltage circuits never get the opportunity to
|| demonstrate this initial period of Crss imbalance, as a 15V change in
|| drain voltage is usually enough to enforce Crss equalization in the
|| totem-pole structure in a 36volt wafer process-limited system.
||
|| RL

Everybody knows this effect and it also occurs with lower voltages.

 

[R.Legg]

|| There are a fair number of articles warning about the effects of dVdT

|| induced turn-on of mosfets due to current induced in Crss. These
|| articles seem to be aimed at recent digital circuit novices
|| struggling with VRMs and are limited to fairly low voltage
|| applications of synchronous buck regulators.
||
|| In higher voltage circuits, where the bidirectional advantages of
|| active switches is attempted in hard switching, the non-linearity of
|| Crss seems to introduce an interesting wrinkle, as it can vary over
|| more than an order of magnitude, depending on the instantaneous value
|| of Vds present through the switching transiion.
||
|| This means that totem-pole structures with identical gate drive
|| circuits will have high dVdt ability when they are just turning on
|| with a high voltage across them, while the recently turned-off
|| switch, with a low voltage across it, will exhibit a Crss almost
|| equal to it's input gate capacity.
||

But also Ciss increases with low voltage and will be always at least double
of Crss.

Ciss changes only by a factor of ~2:1

Crss changes typically by a factor of 50:1

If Crss was half of Ciss, a change of only 5V at high dVdt would be
sufficient to bring Vg up to 2V5, the typical threshold on recent fet
dies.

Theisue is not that a charge is transfered, but that it is transfered
much more quickly as drain voltage rises from 0 to 50V, than it is as
drain voltage falls from 100V to 50V, for a constany dVdT.

If the dVdT is generated by the on-coming switch, the victim part that
attemps t maintain it's off state is subject to both conditions of
maximum dVdt and maximum charge transfer, simultaneously.

|| While the larger Crss does reduce considerably as it's drain is
|| pulled up to >10V by the oncoming switch, the dVdT created by the
|| fast on-coming switch can produce relatively massive curent flow
|| into the gate, easily charging Cgs to the threshold, if not suitably
|| shunted.
||
If you switch the FET on, the resulting gate voltage will have a step form.

This step is at the gate threshold and is maintained solely by current
in Crss. The voltage generated in the 'off' part of the totem pole
does not have a similar restriction, and can be pulled above the
threshold if clamping is insufficient.

when the conduction starts and the switched voltage across the device drops
down, there is charge injected into the gate accordingly. when this charge
is neutralized the gate voltage rises to its static value
The observed high current doesn't come from shoot-through but is the
source/drain-charge flowing to gnd in a few ns.

Drain current flow does not affect gate current or gate voltage - if
the gate voltage threshold is present, drain current flows without
respect to Vds. In this higher voltage case, as much as 1/2 of the
supply rail is formed across the victim 'off' switch of the totem
pole, and more than 1/2 of the supply rail is still present across the
on-coming switch, for the first 10 to 20nSec (or more) of the fall
time.

|| While the resulting shoot-through current is admitedly of short
|| duration, given that the current will fall to a manageable level as
|| the voltages across the two devices and their Crss values become
|| equal in some tens of nanoseconds, the current available during this
|| time can be quite large. The resulting power loss can also be
|| signifigant.
||
|| This suggests that the gate pull-down current capability of the
|| drivers must be some order of magnitude larger that the gate turn-on
|| current; that standard safety margins of 6:1, that are intended to
|| compensate for nonsymetrical drive amplitudes around the gate
|| threshold and an approximately 'linear' Crss, will be ineffective.
||

Exactly that is the reason to put a diode(pointing away from the gate)
across the gate resistor. You will see in the data-sheets that the turn-on
time is much smaller than the turn-off time. So if you slow turn-on with a
resistor and discharge the gate through a diode, you will have
break-before-make in a bridge constallation.

Because typical drivers have fairly high internal resistance (fet
structures)that is typically equal for both drive conditions, even a
6:1 ratio of on/off drive limiting impedances is rare, unless buffered
externally.

In the case of the HV shoot-through, ratios of 20:1 seems almost
effective in avoiding the condition, however the pull-down case can be
severely limited by the actual capabilities of the bipolar
semiconductors performing the pull-down function, both in speed and in
dynamic saturation voltage.

|| Has anyone else out there run into this problem when operating
|| mosfets at higher voltages, when the full range of Crss is
|| experienced? Obviously this is not a soft-switching circuit I'm
|| talking about - but hard switching is still a factor in many
|| commercial circuits, under one condition or another, even when soft
|| switching is attempted, or as an ancilliary to producing an assisted
|| transition employing smaller and faster switches outboard of the
|| main power train.
||
|| I expect that lower voltage circuits never get the opportunity to
|| demonstrate this initial period of Crss imbalance, as a 15V change in
|| drain voltage is usually enough to enforce Crss equalization in the
|| totem-pole structure in a 36volt wafer process-limited system.

Everybody knows this effect and it also occurs with lower voltages.

You do not exibit an understanding of the issue of non-linear Crss
effects in the hard switching totem pole. Please look at a data sheet
for a >100V device and crunch some numbers.

If you are thinking of any condition in which the Vds voltages are
allowed to equalize before switching is performed, then this effect
will not be visible.

RL

 

[Winfield Hill]

legg wrote...

While the larger Crss does reduce considerably as it's drain is pulled
up to >10V by the oncoming switch, the dVdT created by the fast
on-coming switch can produce relatively massive curent flow into the
gate, easily charging Cgs to the threshold, if not suitably shunted.

While the resulting shoot-through current is admitedly of short
duration, given that the current will fall to a manageable level as
the voltages across the two devices and their Crss values become equal
in some tens of nanoseconds, the current available during this time
can be quite large. The resulting power loss can also be signifigant.

I'm going to largely deny this effect, at least as you've stated it.

FET manufacturers rarely show the Crss plots above 25V, leaving one
to imagine that it's flat to higher drain voltages. But that's not
at all the case. I have measured many different high-voltage FET
types while exploring this issue, and have found that in fact Crss
continues to decline, generally dropping to very low values.

In my experience, if single high-value FET gate resistors are used in
an H-bridge or half-bridge, a short period of shoot-through may occur.
It's not easy to measure the shoot-through current, but it's easy to
see the dramatically-increased circuit ringing voltages caused by the
current spike. The effect is similar to that of the current spikes
that occur during the reverse-recovery time of a FET substrate diode.
By actual measurements I have found that generally very little power
loss is involved, but the safety of the FET gates is threatened and
severe RFI emission can occur.

In my experience with slowed H-bridge FET switching, a 3x smaller
gate-discharge resistance is low enough to stop shoot-through; if
this is true, a 6x rule of thumb should be sufficient. Also in my
experience, high gate-current drive can prevent shoot-through, even
with single gate-drive resistors, if the gate-drive current is high
enough to get FET switching speed down to the sub-20ns region. This
conclusion is buttressed by many examples given in H-bridge driver-IC
manufacturer's application notes showing a direct connection of the
driver to the FET gates, a condition which means the FET gates have
equal charge and discharge currents.

However, if one wants to slow FET switching speed with a high-value
gate resistor, why not simply use a parallel Schottky diode with no
series resistor for the discharge path? High-performance driver ICs
include a turn-on delay provision, which it seems to me to eliminate
any motivation to slow down the FET gate's turnoff, because after
turnoff there is no low-resistance path to rapidly take the drain to
the other supply rail. In the case of resonant switching, inductive
currents gracefully carry the FET toward the other rail.

Finally, I'll observe that these rapid-switching situations are very
difficult to model with any confidence using Spice, in part because
the distributed nature of a power MOSFET's gate-spreading resistance
is included in the models.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Winfield Hill]

Winfield Hill wrote...

Finally, I'll observe that these rapid-switching situations are very
difficult to model with any confidence using Spice, in part because
the distributed nature of a power MOSFET's gate-spreading resistance
is included in the models.

----^----
is NOT included in the models.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[R.Legg]

legg wrote...

I'm going to largely deny this effect, at least as you've stated it.

FET manufacturers rarely show the Crss plots above 25V, leaving one
to imagine that it's flat to higher drain voltages. But that's not

CRSS is depicted graphically for typical values, in most data sheets
up to the device rating.

at all the case. I have measured many different high-voltage FET
types while exploring this issue, and have found that in fact Crss
continues to decline, generally dropping to very low values.

In my experience, if single high-value FET gate resistors are used in
an H-bridge or half-bridge, a short period of shoot-through may occur.
It's not easy to measure the shoot-through current, but it's easy to
see the dramatically-increased circuit ringing voltages caused by the
current spike. The effect is similar to that of the current spikes
that occur during the reverse-recovery time of a FET substrate diode.
By actual measurements I have found that generally very little power
loss is involved, but the safety of the FET gates is threatened and
severe RFI emission can occur.

My measurements recently showed currents ramping easily to >20A in
tens of nanoseconds. Even at a duty cycle of 1/400, this current gives
rms values in the 100s of mA range, producing power loss that is a
product of the total supply voltage. This easily accounts for
unbudgetted power lost in the stage.

Don't you ever wonder why things aren't as efficient as is predicted
by book values?

In my experience with slowed H-bridge FET switching, a 3x smaller
gate-discharge resistance is low enough to stop shoot-through; if
this is true, a 6x rule of thumb should be sufficient. Also in my
experience, high gate-current drive can prevent shoot-through, even
with single gate-drive resistors, if the gate-drive current is high
enough to get FET switching speed down to the sub-20ns region. This
conclusion is buttressed by many examples given in H-bridge driver-IC
manufacturer's application notes showing a direct connection of the
driver to the FET gates, a condition which means the FET gates have
equal charge and discharge currents.

This is a fallacy for most drivers, particularly with mos outputs.
Their internal resistance is often the same for pull-up and pull down
from a supply that is unequally distributed around the 2V5 threshold.

This results in unbalance towards turn-on gate current.

You know what you can do with most app notes. A little salt helps.

However, if one wants to slow FET switching speed with a high-value
gate resistor, why not simply use a parallel Schottky diode with no
series resistor for the discharge path? High-performance driver ICs
include a turn-on delay provision, which it seems to me to eliminate
any motivation to slow down the FET gate's turnoff, because after
turnoff there is no low-resistance path to rapidly take the drain to
the other supply rail. In the case of resonant switching, inductive
currents gracefully carry the FET toward the other rail.

Providing that the driver impedance does not dominate, this is one way
of compensating for a typical drive imbalance. The question is whether
or not a 50:1 ratio of CRSS values can practically be compensated for,
while still maintaining a reasonable turn-on speed.

If there is no model that includes these non-linear parameters, then
I'm not suprised there's been little written about it. A Mosfet Mfr is
hardly going to bring up the subject, at least not before they've got
a cure already in the pipeline. Universities seem to depend on
modelling vs lab nowadays.

Rob

 

[R.Legg]

Winfield Hill wrote...
----^----
is NOT included in the models.

Thanks,
- Win

whill_at_picovolt-dot-com

Perhaps it's worth sticking one in.

http://www.orcadpcb.com/pspice/applicationnotes/tn09.asp?bc=F

RL

 

[Winfield Hill]

R.Legg wrote...

Winfield Hill wrote ...

CRSS is depicted graphically for typical values, in most data sheets
up to the device rating.

What? Then why did I spend so much time building an apparatus and
taking measurements? A quick check of datasheets from some of the
primary FET manufacturers (Fairchild, Infineon, IRF, Philips, ST,
ON Semi/Motorola, Vishay/Siliconix, IXYS, Hitachi, and Zetex along
with RCA/Harris/Intersil) shows a 25, 40 or 50V limit for most of
the typical curves. Here and there are curves to 100V, and a few
examples to the rated voltage for high-voltage FETs, specifically
in one data sheet by Infineon, plus I remember seeing a few others
at one time or another. Furthermore, the data shown is rarely in
log-log form, so that the low values in the higher-voltage region
can't be easily picked off the graph. An example of how the real
capacitance data looks can be seen in IRF's an-1001 app note,
http://www.irf.com/technical-info/appnotes/an-1001.pdf You might
argue that there's a wide variation in Cgd with drain voltage, I'd
argue at high voltages it gets so small you can nearly ignore it!

My measurements recently showed currents ramping easily to >20A in
tens of nanoseconds. Even at a duty cycle of 1/400, this current
gives rms values in the 100s of mA range, producing power loss that
is a product of the total supply voltage. This easily accounts for
unbudgetted power lost in the stage.

High currents can certainly be expected after the first 20ns or so,
and in poor designs shoot-thro can last a long time and consume lots
of power. However in the cases I've encountered it has been so short
that the power-loss involved was modest. For example, an H-bridge
operating with no load should ideally have very low currents from the
predictable capacitance charging, and this is what I usually observe.
But while an extra 5W to 10W from shoot-thro in a 500W bridge is low
in terms of its one to two percent power loss, when considered as an
additional 10W of FET heating it may be a real pain. We both agree
it's highly undesirable.

This is a fallacy for most drivers, particularly with mos outputs.
Their internal resistance is often the same for pull-up and pull down
from a supply that is unequally distributed around the 2V5 threshold.
This results in unbalance towards turn-on gate current.

With the exception of logic-threshold power FETs, I largely disagree.
Most power MOSFETs have 4 to 6V Miller-plateau gate voltages during
high-current switching, which is one consideration. More importantly,
the MOSFETs within power-FET-driver ICs are not well characterized as
simple Ron resistances when their drain voltages exceed about 2 to 3V;
here the driver FETs are approaching their saturated regions and are
better described as current sources. This effect is clearly seen in
the data curves for most power FETs, and for various CMOS logic ICs,
but sadly most driver-IC manufacturers don't provide the relevant Iout
vs Vout curves. The Siliconix driver data sheets show a hint of what
I'm talking about. (My point may not be true for some bipolar-output
FET-driver ICs, but most of their data I've seen is unclear on this.)

You know what you can do with most app notes. A little salt helps.

Indeed, and high on the list I'd place the seriously-defective analysis
in the Fairchild AN-6003 "shoot-through" app note. :>)

Providing that the driver impedance does not dominate, this is one way
of compensating for a typical drive imbalance. The question is whether
or not a 50:1 ratio of CRSS values can practically be compensated for,
while still maintaining a reasonable turn-on speed.

I think the annswer is clearly yes. One place most FET manufacturers
do address non-linear capacitance is the gate-charge curves, where in
the fully-ON region we see curves for different drain voltages, usually
including one for 80% of the rated voltage. We can use these to help
evaluate turned-off FET gate-steps from high drain-voltage dV/dt.

Let's pick a FET to clarify the discussion, Fairchild's FQP6N90, a
900V 6A part: http://www.fairchildsemi.com/pf/FQ/FQP6N90.html

Here we see that about 4pC of gate charge from Cgd is required to go
from a drain voltage of 180V to 720V. Compare this to 9pC of charge
required to turn on the FET's gate from 0V; there's not enough charge
from the 540V drain-voltage change to do it, even assuming a floating
gate and an infinite dV/dt. In reality dV/dt is usually slower than
say 50V/ns (i.e. 500V in 10ns, picked for Ciss * Rg = 9ns with Rg = 6
ohms), and we see that a FET driver, with a reasonably-low resistance
to ground, usually has sufficient time and moxie to control gate step
and thereby avoid serious noticeable shoot through, or to keep it to
a short time and a modest current, similar to the current spike from
charging Coss.

If there is no model that includes these non-linear parameters, then
I'm not suprised there's been little written about it. A Mosfet Mfr is
hardly going to bring up the subject, at least not before they've got
a cure already in the pipeline. Universities seem to depend on
modelling vs lab nowadays.

Whooaa, there Mr. Legg! Most spice FET models certainly do include
non-linear capacitance, just as do spice diode and BJT models. Kevin
and others can speak with more authority than I, but multiple types
of non-linear capacitance and charge models have long been standard in
spice, reaching a high level of sophistication as far back as the Meyer
models of 1971. Including both analytic and lookup-table types, and
hybrids of these. Some power MOSFET models, following suggestions by
CF Wheatley and HR Ronan (from RCA days) to add an internal depletion-
mode JFET inside the MOSFET to greatly improve non-linear accuracy at
low voltages. E.g., see Harris AN8610 --> Fairchild AN7506 app note.
http://www.fairchildsemi.com/an/AN/AN-7506.pdf

But you missed my point: it's not poor non-linear capacitance modeling
that makes typical power MOSFET models so poor for evaluating dV/dt in
the sub 20ns region, it's the use of lumped elements where distributed
ones are needed.

For example, a step change in the gate voltage may be immediately seen
by perhaps 10% of the FET area, more after 5ns and more yet in another
5ns, with still more time required for 100% of the FET to see the gate-
voltage change. This is the realm of gate-spreading resistance, which
is very poorly modeled as a single lumped resistor.

A proper gate-spreading resistance model may be critical for analysing
shoot-through possibilities. For example in a rapidly-switched bridge
the turned-off FETs may have little time to build up significant current
flow. Alternately a portion of the FET gate may be so isolated from the
gate pin that the external driver can't control it. Clearly basic gate-
resistance properties of the FET are needed to evaluate its performance.
This interest me, so I have devoted some time and energy exploring and
taking measurements. For the FETs I've evaluated, the gate resistance
has been surprisingly low, far below the values typically seen in some
manufacturer's spice models. Here one often finds a throw-away value
like 50 ohms, which is clearly totally wrong and basically useless. A
few power MOSFETs specify Rg, and values like 2 ohms are not uncommon.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Winfield Hill]

R.Legg wrote...

Winfield Hill wrote...

Perhaps it's worth sticking one in.
http://www.orcadpcb.com/pspice/applicationnotes/tn09.asp?bc=F

Interesting, but that's not a gate-spreading resistance model.
In the past I've kludged one by breaking the FET into 5 parts and
adding increasing gate resistance for some of the parts, but ...

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Ban]

Winfield Hill wrote:
|||| In my experience with slowed H-bridge FET switching, a 3x smaller
|||| gate-discharge resistance is low enough to stop shoot-through; if
|||| this is true, a 6x rule of thumb should be sufficient. Also in my
|||| experience, high gate-current drive can prevent shoot-through, even
|||| with single gate-drive resistors, if the gate-drive current is high
|||| enough to get FET switching speed down to the sub-20ns region.
|||| This conclusion is buttressed by many examples given in H-bridge
|||| driver-IC manufacturer's application notes showing a direct
|||| connection of the driver to the FET gates, a condition which means
|||| the FET gates have equal charge and discharge currents.
|||
||
|| But you missed my point: it's not poor non-linear capacitance
|| modeling that makes typical power MOSFET models so poor for
|| evaluating dV/dt in the sub 20ns region, it's the use of lumped
|| elements where distributed ones are needed.
||
|| Thanks,
|| - Win
||
|| whill_at_picovolt-dot-com

When I tested my H_bridge, I first returned the capacitors to gnd directly
and always had the overcurrent protection triggered even at low load
currents. I also first thought there is a shoot through, but it happened
even when I increased the dead-time. It is just the bridge arm capacitance
that discharges within 20ns and gives peaks up to 30A in my case, limited
only by the R_DSon. I then returned the capacitors as shown and could
eliminate this current flowing through my current measure resistor.

60V
o
|
+-------+-------+------+------+
| | | |
| ||-+ +-|| |
| ||<- ->|| |
| -||-+ +-||- |
| | | | 4u7||0u1
4u7||0u1 | | ___ | ---
--- +--+-|___|-+---+ ---
--- | R_LOAD | |
| | | |
| ||-+ +-|| |
| ||<- ->|| |
| -||-+ +-||- |
| | | |
+-------+-------+------+------+
|
.-.
| |
| |0R033
'-'
|
|
===
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

 

[R.Legg]

R.Legg wrote...

What? Then why did I spend so much time building an apparatus and
taking measurements? A quick check of datasheets from some of the
primary FET manufacturers (Fairchild, Infineon, IRF, Philips, ST,
ON Semi/Motorola, Vishay/Siliconix, IXYS, Hitachi, and Zetex along
with RCA/Harris/Intersil) shows a 25, 40 or 50V limit for most of
the typical curves.

I can only refer to the sheets I'm currently dealing with. IR seems to
have no problem depicting the full plot for typical crss values for
devices above 100V. Publications prior to 1995 aren't so obliging,
I'll admit.

Here and there are curves to 100V, and a few
examples to the rated voltage for high-voltage FETs, specifically
in one data sheet by Infineon, plus I remember seeing a few others
at one time or another. Furthermore, the data shown is rarely in
log-log form, so that the low values in the higher-voltage region
can't be easily picked off the graph. An example of how the real
capacitance data looks can be seen in IRF's an-1001 app note,
http://www.irf.com/technical-info/appnotes/an-1001.pdf You might
argue that there's a wide variation in Cgd with drain voltage, I'd
argue at high voltages it gets so small you can nearly ignore it!

In the totem pole configuration, both maximum and minimum capacitance
exists in the situation where the junction between the two parts is
close to one supply.

The on-coming fet is subject to the minimum, and can attempt to
produce a drain dV/dT under the influence of gate current and the
minimum value. This dV/dT however is impressed upon the off fet that
has the initially lower drain voltage. If the ratio of Crss is 30:1,
then the ratio of gate currents will be similar, for a fixed dV/dT,
shared by both parts.

High currents can certainly be expected after the first 20ns or so,
and in poor designs shoot-thro can last a long time and consume lots
of power. However in the cases I've encountered it has been so short
that the power-loss involved was modest. For example, an H-bridge
operating with no load should ideally have very low currents from the
predictable capacitance charging, and this is what I usually observe.
But while an extra 5W to 10W from shoot-thro in a 500W bridge is low
in terms of its one to two percent power loss, when considered as an
additional 10W of FET heating it may be a real pain. We both agree
it's highly undesirable.

I was measuring values that contributed considerably to losses in a
circuit that had the potential to be quite efficient. Of course it
wasn't.

With the exception of logic-threshold power FETs, I largely disagree.
Most power MOSFETs have 4 to 6V Miller-plateau gate voltages during
high-current switching, which is one consideration. More importantly,
the MOSFETs within power-FET-driver ICs are not well characterized as
simple Ron resistances when their drain voltages exceed about 2 to 3V;

This is exactly how they are characterized. Peak rated current being
the current available into a short, but not necesarily into a
capacitor charged to 1/2 the supply. There is always some bending with
numbers going on between typical and maximum.

here the driver FETs are approaching their saturated regions and are
better described as current sources. This effect is clearly seen in
the data curves for most power FETs, and for various CMOS logic ICs,
but sadly most driver-IC manufacturers don't provide the relevant Iout
vs Vout curves.

That saturated V/I characteristic of a mosfet IS a resistance. The
current only plateaus outside of the saturation region, where for a
fixed Vg, Id remains relatively constant.

The Siliconix driver data sheets show a hint of what
I'm talking about. (My point may not be true for some bipolar-output
FET-driver ICs, but most of their data I've seen is unclear on this.)

Bipolar outputs can generate a guaranteed constant current over the
compliance output. Mos outputs can't due to output saturation
resistance. This is off-topic.

Indeed, and high on the list I'd place the seriously-defective analysis
in the Fairchild AN-6003 "shoot-through" app note. :>)


I think the annswer is clearly yes. One place most FET manufacturers
do address non-linear capacitance is the gate-charge curves, where in
the fully-ON region we see curves for different drain voltages, usually
including one for 80% of the rated voltage. We can use these to help
evaluate turned-off FET gate-steps from high drain-voltage dV/dt.

I am currently restricted to turn-on speed values that significantly
affect the function of the circuit section. This function is to
hard-switch at low power, to provide soft-switching on another
larger-power node. The larger node is soft switched because it may
have lousy forward biased rectifiers present or be subject to other
dV/dT and dI/dT restrictions. We count on the low power node to switch
fast without misbehaviour, and parasitics are controlled to a large
degree.

Let's pick a FET to clarify the discussion, Fairchild's FQP6N90, a
900V 6A part: http://www.fairchildsemi.com/pf/FQ/FQP6N90.html

An interesting example, but it looks like a typo on the voltage scale
- this is the scale normally used for On-Region characteristics. IR
charts start at 1V. For low voltage parts used in synchronous
rectification, the lower and reverse voltage characteristics might be
useful. The linear capacitance scale is also poorly chosen.

Here we see that about 4pC of gate charge from Cgd is required to go
from a drain voltage of 180V to 720V. Compare this to 9pC of charge
required to turn on the FET's gate from 0V; there's not enough charge
from the 540V drain-voltage change to do it, even assuming a floating
gate and an infinite dV/dt.

In the totem pole configuration, the typical Crss value of 17 pf
published for this part should allow an initial dV/dT of 58820v/uSec
for at least the first 20V of mutual change in drain voltage, with the
gate fixed at it's threshold, charging Crss from a 1A drive source.

If the on-coming fet were capable of delivering it, this dV/dt,
occuring for only 0.2nSec, would generate gate currents in the 'off'
fet Crss ranging from;
35A (first 50pSec to 2V5 at 600pF); (charge transfered 35Ax50pSec =
1.75nC)
17A (second 50pSec to 5V @ 300pF); (charge transfered 17Ax50pSec =
..85nC)
12A (third 50psec interval to 7V5 @200pF); (charge 12x50pSec = .6nC)
through to
5A(last 50pSec to 10V @100pF). (charge transfered 5Ax50pSec = .25nC)

i = dQ/dT idT=dQ

A first-approximation charge transfer (i.t)of >3.3nC could occur in
this time. Would this have charged the off fet's ~2000pF input
capacity to it's gate threshold? No, the input capacitance would have
charged to only 1.6V.

This impulse was produced in a fet designed with low Crss - the 'QFet'
series.
The ratio of Crss over the voltage range was still roughly 50:1
(C1V/CratedV) for this part, which I had determined is the problem.

I guess that's not it.

In reality dV/dt is usually slower than
say 50V/ns (i.e. 500V in 10ns, picked for Ciss * Rg = 9ns with Rg = 6
ohms), and we see that a FET driver, with a reasonably-low resistance
to ground, usually has sufficient time and moxie to control gate step
and thereby avoid serious noticeable shoot through, or to keep it to
a short time and a modest current, similar to the current spike from
charging Coss.

This example used 50V/nsec

Whooaa, there Mr. Legg! Most spice FET models certainly do include
non-linear capacitance, just as do spice diode and BJT models.

Misread your comment to indicate that non-linear capacitance element
was not included in most models, not gate resistance.

I have little faith in modeling, and keep away from it, where
possible. Sometimes it is neccessary hairy persiflage, as people seem
to be willing to believe the compeeoodah, when they won't believe the
low-priced help.

RL