unused pins on 4093 IC- what to do with them?

[Will Waterston]

I am building a small circuit that uses this 4093 ic, but I am only using
pins 1-7 and pin 14 of course for power. Pins 8-13 are not being used.
What should I do with these pins? Since I am using a socket, I was going to
just clip these pins so they wouldn't be part of the circuit board and just
solder in pins 1-7 and 14, but now I'm coming across readings that there
should be no pins left open with this IC since it is CMOS. Can I leave
these pins open and, if not, should I just ground them or pull them to
ground with a 3-5K resistor?

Thanks in advance,
Will

 

[mkaras]

I am building a small circuit that uses this 4093 ic, but I am only using
pins 1-7 and pin 14 of course for power. Pins 8-13 are not being used.
What should I do with these pins? Since I am using a socket, I was going to
just clip these pins so they wouldn't be part of the circuit board and just
solder in pins 1-7 and 14, but now I'm coming across readings that there
should be no pins left open with this IC since it is CMOS. Can I leave
these pins open and, if not, should I just ground them or pull them to
ground with a 3-5K resistor?

Thanks in advance,
Will

Unused logic inputs to CMOS chips should generally not be left open.
(The only case where it is ok is in those where the manufacturer has
designed in some on-chip pullup or pulldown scheme). In the case of
this part the inputs to your spare gates should be tied to a
legitimate logic high or logic low level. For simplicity on a hobby
type project it would be suitable to simply ground pins 8 & 9 and also
12 & 13. Do not ground pins 10 and 11 since these are outputs and part
damage could occur if you did so.

For the inputs you could actually do any of:
- ground as suggested
- pull down to ground via a resistor
- tie direct to VDD (same rail as pin 14)
- pullup to VDD through a resistor
- tie the pins to some other logic device output that is at a known
idle level as a high or low.

- mkaras

 

[Tim Wescott]

Unused logic inputs to CMOS chips should generally not be left open.
(The only case where it is ok is in those where the manufacturer has
designed in some on-chip pullup or pulldown scheme). In the case of
this part the inputs to your spare gates should be tied to a
legitimate logic high or logic low level. For simplicity on a hobby
type project it would be suitable to simply ground pins 8 & 9 and also
12 & 13. Do not ground pins 10 and 11 since these are outputs and part
damage could occur if you did so.

For the inputs you could actually do any of:
- ground as suggested
- pull down to ground via a resistor
- tie direct to VDD (same rail as pin 14)
- pullup to VDD through a resistor
- tie the pins to some other logic device output that is at a known
idle level as a high or low.

On a production board it is often wise to pull the inputs up or down
through resistors. That way if you need a spare gate you'll be able to
get to it without lifting pins -- I always try to design my boards to
make greenwire mods easy.

If you're _really_ paranoid you'll bring the spare outputs out to vias
or pads, to have them available, too.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

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