[Rui Monteiro]

Hey everyone,

Some months ago I started to learn by myself electronics, so my level of knowledge is probably basic.

I'm projecting on multisim one ESR meter. Basicaly the big diference between my project and others we can find on Internet is that mine is intended to work with one frequency of 20 MHz (sine wave). My oscilattor is one colpitts transistor oscilattor, inductor one. After this I have one buffer and amplifier to inject the signal into the cap under test, using one constant current source. Because, frequency is very high, the reactance of the capacitor under test will be very low, thus the final impedence will be aproximatly the ESR value for the lowest cap of 1uF. Now that we know the resistance of the circuit under test and we also know the current, lets say 100uA, the voltage at the the capacitor terminals will be aproximatlly one multiple of ESR value. To measure this voltage, since I cant find one opamp with high gain at this frequencies, I'm amplifing the voltages at the cap terminals with transistors. Now I need to transform the ac voltage peak to peak into one equivalent dc voltage, to make one opamp instrument amplifier to excite one voltimeter. So I am trying to implement peak detector with one pin diode in series with one parallel capacitor and resistance. And this is where the issue happens. Whenever I link the peak detector with the previous circuitry, after turn the simulation on, the 20MHz disapear and it seems that appear for some short periods of time others oscilations with low amplitude. If I disconnect the peak detector from the circuit, everything seems to be working fine.

Does anyone know what could be wrong? I suspect that for some reason I dont know, part of the colppitts oscilations are being absorved via ground by the peak detector, but as I said before, I'm rookie in this kind of stuff and I really dont know how to solve this issue.

I will aprecciate every help. Thank you very much in advance.
Rui

 

[(*steve*)]

If you're simulating, you need to ensure that the simulation accounts for ESR in the capacitor. Also 20MHz is a very high frequency for an ESR meter and is going to make your circuit more of an RF design that you probably want. 100kHz is actually a standard frequency to do ESR tests since ESR is frequently specified at this frequency.

Once you reduce the frequency your peak and hold circuit will be far simpler.

Perhaps if you can show us your circuit we can give you some more hints.

 

[Rui Monteiro]

Hey (*steve*),

Thank you very much for your reply.

I know that the standard frequency for the measurements is more or less 100KHz, but with this kind of frequencies for low values of ESR the total impedence (CAP + ESR) tends to be the reactance values of the capacitor. This way, for low values of ESR the nedlle tends to move in short degrees, and for higher values higher degrees, thus the scale tend to be not linear. So I thought I could raise up the frequencie so the reactance became lower than the 10mΩ of the lowest value of ESR I expect to measure. This way I will have one more linear scale measurements.

For the simulation purposes, I'm simply using one resistor in series with one capacitor.

I will post here soon the circuit I already planned for your analyses.

Thank you very much.

 

[Rui Monteiro]

Hey fellows,

I promissed in my previous post one shot of my ESR plan until now. Here it goes:


I really hope that this could help. Once again I thank you all.

 

[(*steve*)]

Can you explain the purpose of R40?

 

[Rui Monteiro]

Of course.

R40 is there only for simplification of the circuit. Since ESR meters can measure caps in circuit, the total voltage I'll have is about 150mV. With R40 in place the total current is more or less 100μA. In the future, R40 is to be substituted with one FET transistor wich will vary is ohmic value as needed to ensure constant 100μA. Thats the why I have in the circuit R15 (sense) to measure also its voltage to control the JFET.

 

[(*steve*)]

R40 seems to be in series with the ESR of the cap. Won't the effect of the this resistor swamp out the effect of the ESR on the voltage at the point labelled 16 in the circuit?

 

[Rui Monteiro]

You're right. I forgot to mention that the buffer + amplifier connected to the point 16 are only there to measure peak to peak voltages at that point. other similar circuit will be connected to the point 14 with same function. The purpose of this is to subtract both voltages, the result will be the voltage peak to peak produced by ESR capacitor. All of this could be much easier if I could make some diferential amplifiers opamp based, but as I have mentioned before, it is not so easy to find cheap high gain opamps to work with 20 MHz frequencie...

 

[(*steve*)]

Have you considered my comments on the use of such a high frequency?

Is the ESR at that frequency actually meaningful for you?

 

[Rui Monteiro]

Once again, thank you Steve for your reply.

The main reason I am considering using this frequencie is to create one linear scale of outputs readings. This way I will be able to use one digital voltimeter for the output readings. Other reason is to raise the accuracy of the readings.

To ilustrate this lets make some maths. Consider that we already have 2 ESR meters. One will operate with 100 KHz and the other with the 20 MHz. Lets consider also that we will measure one capacitor of 1μF with one known ESR lets say hipoteticaly of 10mΩ. If we apply the test probs of each ESR meter to this capacitor, we will be measuring the final impedence of the ESR in series with the capacitor itself. So:

Z = SQR(ESR^2 + Xc^2) and Xc = 1 / (2 *pi * f * C)

Lets see what Values we will have for Xc for both frequencies:

Xc(100Khz) = 1 / (2 * 3.14 * 100 000Hz * 0.000 001F) <=> Xc(100Khz) =1.5915Ω

Xc(20 Mhz) = 0.0079577Ω <=> Xc(100Khz) =7.9577mΩ

Now lets do maths for the impedences:

Z(100 Khz) = SQR(0.01^2 + 1.5915^2) <=> Z(100 Khz) = 1.59158Ω

Z(20 Mhz) = SQR(0.01^2 + 0.0079577^2) <=> Z(20 Mhz) = 0.0127798Ω (very accurate measure of ESR)

Now if we apply the current of 100μA (peak to peak) using both frequencies to the cap under test:

V(100Khz) = 1.59158Ω * 0.0001 <=> V(100 Khz) = 159.158μV

V(20 Mhz) = 0.0127798Ω * 0.0001 <=> V(20 Mhz) = 1.27798μV

As you can see, we will have much closer results to the reality especially with low values of ESR and C with the 20 MHz rather than 100 KHz ESR meter. If we want to use the 20 MHz voltage, we can easily amplifie these voltage in multiples of 10 and we will obtain one voltage that will seem to be the ESR value of the cap under test. So if we use in this application one voltimeter with 2 decimal numbers for the lower value of ESR expected to measure as 10 mΩ, we will obtain one output reading of 00.01 wich will correspond to 10 mΩ of ESR. If you continue to make maths for higher values the error will be even lower and the accuracy of the measurements will rise substantially. Also the scale will be very linear.

Probably I am demanding to much accuracy for one ESR meter, but it can be used also to measure with high precision low resistors for instance...

What do you think about it? Thank you very much!

Note: I ask for sorry about my poor english, but believe me I am trying to write the best I can.

 

[(*steve*)]

ESR is frequency dependant, so measuring the ESR at different frequencies is going to give you different results. A large measure of this is due to the fact that inductance forms a part of ESR, and one that will rapidly become more significant at higher frequencies. However some component of the ESR is also resistive. The resistive component will be swamped by the inductive component as the frequency rises. Measuring at 100kHz is reasonable because you're doing it in the range of frequencies that are likely to be met. If you are planning to use a capacitor in a SMPS operating at 3MHz, then it might be reasonable to measure the ESR at these elevated frequencies.

Your aim of 100μΩ resolution is laudable, but will you be able to achieve it? Have you considered the resistance of your wiring (which can be cancelled out) and the resistance of the connections to your capacitor (which can't as easily be cancelled out)?

Switching a square wave at 20MHz is also going to have significant components up to 200MHz and beyond.

I would recommend you use a lower frequency, amplify the AC component of the voltage across the capacitor (perhaps measured using a 4 wire method to try to eliminate connection resistance) before doing a peak and hold on this.

If you plan to continue with the 20MHz, then you're really designing a piece of RF equipment and I'm not the best person to assist you.

 

[Rui Monteiro]

Hummm in fact you are right in your considerations about inductive influence in the circuit. But with lower frequencies how can I get linear readings? This is one thing that really worries me...

 

[(*steve*)]

The voltage will always be linearly related to resistance for a given constant current.

 

[KrisBlueNZ]

Hi Rui. Sorry to jump in, but I have a several questions and suggestions. I'm not sure I fully understand the circuit, so some of my criticisms may be wrong. You're lucky you have Steve helping you with this; his advice is excellent. Actually, he may be able to respond to my comments below.

1. R6 is unnecessary and pointless.
2. R8, R9 and C7 can be removed if Q3's base is tied to 0V.
3. I don't understand the point of the Q2/Q3 circuit. You have a variable proportion of the 20 MHz sinewave feeding a JFET whose source is operated at about 5 mA via a constant current sink bypassed with a 1 nF capacitor, operating into a 1k resistor for the drain load. What is this supposed to achieve?
4. Q4 will not produce a low-impedance signal at its emitter; R18 and R14 are far too high, for a start. I think you need something like a complementary pair as used in output stages of audio amplifiers.
5. R17 doesn't need to be 100 MΩ. It can be far lower (and will have to be, if you want to be able to build the circuit with real components!)
6. Comments for Q9 as for Q3.
7. Comments for Q10 as for Q2.
8. Why have you used such low values for the base resistors for Q11, and such a high value for the emitter resistor?

I can't say whether there's any merit in that circuit at all. RF is not my specialty. But I would like to see a circuit description and answers to those points, if you can be bothered.

 

[Rui Monteiro]

Hey Steve.

Thank you very much for your reply once again.

Yes it's true. For any fixed resistance and current the voltage will be linearly. But the point is that we are reading the voltage produced by impedence and not ESR. Since like I have demonstrated before, Xc for lower values of C, will be very often higher than ESR, and this will create for lower values of ESR, fewer variations of final voltage measured on capacitor terminals. The readings on the scale will run more constantly, as soon as Xc may became lower than ESR because z = SQR(ESR^2 + C^2), and for this became true, the ESR meter will be very constant for higher values of C where Xc became lower at 100Khz, or whenever we may found one bad capacitor with to high ESR. That is why I think the readings will not appear linear specially with readings for low capacitance values.

Ok I assume I may be wrong also, as I said before I'm new in electronics and all I know is the result of my own study, so yes, I may be wrong. Please correct me if I may be wrong. Thank you.

 

[Rui Monteiro]

Hello Kris,

Welcome to this friendly conversation about ESR meter project. It's good to know your opinion also. All the bad points we can improve must be reported and I think all of you could be of great help. For sometimes I am too much envolved with the project that I would not see some points that could be evident for experienced people, so feel free to participate whenever you may want and feel necessary. I thank you very much.

Ok lets see if I can explain all points you have mentioned:

1 - «R6 is unnecessary and pointless.» It's true and I think that keep it there will not improve performance of the oscillator since this way, the oscilations passing on R6 wil demand more current from the oscilator and that besides the low values envolved, we are pertubating the oscilator demanding unecessary power. The main reason I put it there was my despair considerations that if the gate of the JFET Q2 where not grounded, that could pertubate the functionality of the circuit. So I put it there just to test if could be this the cause of stoping the oscilations whenever I connect to the final circuit the peak detector. So yes, this resistor can be removed.

2 - «R8, R9 and C7 can be removed if Q3's base is tied to 0V.» Yes and no . Yes your logic its 100% reasonable and correct. Initially my first design was with the base of Q3 grounded (0V) but I found that with this circuit the oscilations of 20 MHz were loss also. So to keep things running I made that circuit to connect to the base of Q3 more or less 0V. The C7 was needed to avoid any oscillations on the base of Q3 to make stable the point Q of Q3.

3 - «I don't understand the point of the Q2/Q3 circuit. You have a variable proportion of the 20 MHz sinewave feeding a JFET whose source is operated at about 5 mA via a constant current sink bypassed with a 1 nF capacitor, operating into a 1k resistor for the drain load. What is this supposed to achieve?» if I connect the emitter follower Q4 directly to the atennuator, the base current of it will be too much high for the oscilator and the oscilations will stop again and in the best case will happen but distorted, so I had the need to buffer it first with the JFET Q2. As you know the gate current will be very little (some pA) and that will not interfere with the current on the atenuator and oscilator. To keep the point Q of Q2 very stable, I puted the transistor Q3 as a current constant sink as you have mentioned. But this circuit will have a very little gain, so to improve gain I had bypassed the source of Q2 to the ground via 1nF capacitor. Q3 acts like an source resistor but if for some reason in the future we have the need to substitute Q2 the Drain current will be constant independently of the JFET used. The 1k resistor (R10) is there to make 2 functions. 1st is to make one drain voltage drop to more or less 4.5V, this way all signals amplified will not distort in a very wide range of voltages. The 2nd is get some gain. Now the drain can be coupled to a circuit emmiter follower (Q4) to inject about 150 mV on the capacitor under test.

4 - «Q4 will not produce a low-impedance signal at its emitter; R18 and R14 are far too high, for a start. I think you need something like a complementary pair as used in output stages of audio amplifiers.» The point of this is to keep output voltage of Q4 the more constant possible. If I couple the ac signal via colector I will get one high impedence output like you have mentioned in other words. I confess I have not tried yet to connect the circuit like this, since at the beggining I haven't considered to keep current constant on the capacitor under test using one JFET to vary it's ohmic resistance whenever needed to keep current constat on 100μA. I just have considered one Resistor R40, considering that the current will remain aproximatly constant for low ESR values of the cap under test. So I thought that if I'll couple the signal from the collector of Q4, I'll be varying the Q4 gain also for different capacitors. This will produce diferent voltages, then different currents for different capacitors, also then, diferent final readings. For high values of ESR will produce less voltages not proporcional to the voltages produced with low ESR values. Coupling the cap under test to the emitter, the gain will stay aproximatly equal to 1 and will vary very little the voltages with diferent loads (caps or resistors). So to this comment of your's I will try to couple the signal to the colector of Q4 and see the results. I'm confident that it will work fine since R40 is to be substituted with one JFET to make one voltage controled resistance with it, thus the final gain will remain constant with the variations of it's Ohmic value to keep current constant. R15 will do the work of sensing the current thruw it, the voltage drop on R15 will control the gate of the JFET on place of R40.

(will continue on next post)

 

[(*steve*)]

we are reading the voltage produced by impedence and not ESR

But you're calling it an ESR meter?!?!?!

Perhaps you need to draw the circuit as you intend it to be so we can see what you're actually doing as you have noted problems in a whole lot of things (differential amplifier for example) that are not shown on this circuit.

If you are using R40 to provide a voltage offset, that's not going to work well either. Better to omit it and use a double ended power supply (real or virtual)

 

[Rui Monteiro]

5 - «R17 doesn't need to be 100 MΩ. It can be far lower (and will have to be, if you want to be able to build the circuit with real components!)» You are correct again. Part of the answer of this is explained on point 1. Other reason for this too high value was to make the ac current trouw it little. This time only for not influence the current on the capacitor under test. In fact it can be removed as also the R6.

6 and 7 - It's the same logic I had puted into point 3.

8 - «Why have you used such low values for the base resistors for Q11, and such a high value for the emitter resistor?» When I was reading the 2n3904 transistor datasheet, found that the best dc current gain will be get using one colector current of 10 mA. This will produce one HFE minimum of 100. So the base current will be in the worst case 100μA. To keep the base voltage divider more constant I assume that the current trouw it will be 100 times higher than the base current. R36 is a little bit lower than R37, because the current on R36 will have also the base current. This imposes one stable Q point on Q11.

I hope that this may have helped you to understand what I have done until now. This is far away to be the final schematics, there is much to do and correct. Now I'am considering very much all the suggestions of steve for now. probably I will do one ESR meter using 100 or 200 Khz for start and will try to improve my knowldgements on RF first and only then return to this project. But I'm anxious and curious in knowing what is causing the stop of oscillations whenever I connect the peak detector...

However I thank you all for all of your's efforts in trying to help me with this project. Any suggestions will continue to be well received and apreciated.

 

[Rui Monteiro]

But you're calling it an ESR meter?!?!?!

Perhaps you need to draw the circuit as you intend it to be so we can see what you're actually doing as you have noted problems in a whole lot of things (differential amplifier for example) that are not shown on this circuit.

If you are using R40 to provide a voltage offset, that's not going to work well either. Better to omit it and use a double ended power supply (real or virtual)

OK steve I think that I haven't explained well Let me try again.

This is not my final schematics for my project. Building it until now, I found some problems that I cannot explain neither understand why they exist at all. My initial post was to try to understand why oscilations have stoped after conecting that peak detector on net 17. But my basic idea was to reduce the effect of Xc to a minimum value so the impedence formula tends for the ESR value and not for the Xc. So the voltage drop on the capacitor under test will be very close to the effect caused by ESR. That's why every ESR meter uses one relative high frequency. But thanks to you, I've learned also that ESR value in reality does not have only a resistive component as I thought initially and incrising too much the frequencie may cause one high value of XL make it more complex to measure as a pure resistive part making its value frequencie dependent. So I'm considering all your opinions from now on and I'm really grateful to you. As I said before to Kris, probably I'll leave this project since I dont have the skills neither the knowledgments necessary to proceed. I will be working on an ESR meter of 100 or 200 Khz test frequencie. It will be much simpler for now.

But once again I thank you all for your kindness and effort in trying to help me. I'm really gratefull. Thank you very much.

 

[(*steve*)]

Firstly I note you are using a double ended power supply, so R40 still seems pointless.

Some months ago I started to learn by myself electronics, so my level of knowledge is probably basic.

You seem to be doing a lot of design for someone with "basic" knowledge. Can you detail your knowledge a little more?

But I'm anxious and curious in knowing what is causing the stop of oscillations whenever I connect the peak detector...

Does your oscillator stop? I'm not sure exactly where you see the oscillations stop.