slew rates, rise time, and EMI

[foTONICS]

So lately I've been diving (a little blindly) into EMI, ways to contain it, and the different components and/or layout of a PCB that contributes to EMI. Yesterday I came across some articles that mention how the rise/fall time of high speed digital signals can contribute to EMI so it's best to try and control the slew rate by rounding off the corners by a bit. Sort of like this:

Is there some sort of standard that is common place in industry?

I assume the rounding is done by capacitors?

What tends to be more noisy, the rising edge or the falling, or are they about the same?

Since these signals are data and have little current I assume they wouldn't be as noisy as the radiated emissions produced by SMPS?

 

[(*steve*)]

Rise and fall time is usually a feature of a logic family. Choosing one with a slower rise and fall time will help reduce EMI.

For example, using a slower logic family will typically contribute to lower EMI.

Picking a logic family with higher noise immunity will allow them to operate with higher noise levels.

 

[foTONICS]

For example, using a slower logic family will typically contribute to lower EMI.

So designers play a balancing game between keeping EMI low and having fast data transfer rates?

 

[(*steve*)]

In some respects, yes. However, lower voltages (e.g. Going from 5v to 3.3v to 1.8v...) allows higher speed and lower power with a constant slew rate.

 

[Harald Kapp]

Definitely.
But slew rate / rise time / fall time is only one side of the medal.
Voltage levels also play a role (achieving a higher voltage level within the sime rise time means higher slew rate and therefore more emitted EMI).

Picking a logic family with higher noise immunity will allow them to operate with higher noise levels.

Very true. This can be achieved e.g. by using differential signalling. Each single signal's amplitude is half of the total, since the difference counts. Half the amplitude makes for reduced slew rate and therefore less EMI.

Another important factor is the layout of the circuit. Here are a few key points to consider (I don't claim this list to be cmplete):

• Keep traces short
• Minimize current loops (see also next item)
• Have a ground plane set up directly below the signal layer allowing for a short return path for the currents
• Maybe use a second ground plane to shield the signals
• Properly terminate high speed traces to avoid reflections and ringing
• Have the ground plane extend a few mm over the outermost signal traces (and/or VCC planes) to minimize emission from the edges
• Ensure proper buffering of the power supply by putting suitable buffer capacitors very near to each consumer (IC)

Plus a few more that may have to be considered case by case.

Also note that EMI is not only a matter of emitted electromagnetic radiation, it is to the same amount a matter of susceptibility to electromagnetic radiation from external sources. One of the reasons while shielded cables are in common use.

And last not least a matter of conducted emissions - vey often a major issue with SMPS.

 

[foTONICS]

Definitely.
But slew rate / rise time / fall time is only one side of the medal.
Voltage levels also play a role (achieving a higher voltage level within the sime rise time means higher slew rate and therefore more emitted EMI).

Very true. This can be achieved e.g. by using differential signalling. Each single signal's amplitude is half of the total, since the difference counts. Half the amplitude makes for reduced slew rate and therefore less EMI.

Another important factor is the layout of the circuit. Here are a few key points to consider (I don't claim this list to be cmplete):

• Keep traces short
• Minimize current loops (see also next item)
• Have a ground plane set up directly below the signal layer allowing for a short return path for the currents
• Maybe use a second ground plane to shield the signals
• Properly terminate high speed traces to avoid reflections and ringing
• Have the ground plane extend a few mm over the outermost signal traces (and/or VCC planes) to minimize emission from the edges
• Ensure proper buffering of the power supply by putting suitable buffer capacitors very near to each consumer (IC)

Plus a few more that may have to be considered case by case.

Also note that EMI is not only a matter of emitted electromagnetic radiation, it is to the same amount a matter of susceptibility to electromagnetic radiation from external sources. One of the reasons while shielded cables are in common use.

And last not least a matter of conducted emissions - vey often a major issue with SMPS.

I've noticed on some PCB's that a line of vias extend around the perimeter of the board, going down to what I assume to be the grounding layer. If this helps EMI why don't I see it more often? Is it a last ditch effort to contain EMI?

 

[Harald Kapp]

There may be several reasons, one of them EMI. It may also have to do with minimizig the impedance to lower voltage drop. Or something else. It depends on the specific layout. Generally one can say that there is no general rule for good EMI proof design. What works in one design may (or may not) be counter-productive in another design.
And then there's always cost to be taken into account. More layers, more vias more money