I'm build a shift register with D-latches and have a question. In theory, if the propagation delay time of each latch is less than that of the clock's mark time, then will it not end up accidentally turn on multiple latches and cause a major glitch?
So I have a multiplexer, and the datasheet for it. Now to assist users in use the datasheet contains a logic diagram, which would be much more useful if I knew what this was...
That's my rendition of it. Note that it has 4 ins/outs, one from each side's center. Any ideas?
Also, HEF4053BP is...