ACTEL A54SX32 inout

[nicolas]

For a A54SX32A ACTEL projet developped on ACTEL LIBERO:
For a vhdl module, i use tow input-output port (inout: DATABU8S and
DQ), like a transceiver.
it vhdl implementation is like this:
*
* DQGESTIONrocess(WEBBUS,REBBUS,DQ,DATABUS,CEBBUS)
* begin
* if (WEBBUS='0' and CEBBUS='0') then
* DQ <=DATABUS; --ecriture sur la
SDRAM
* DATABUS <=(others=>'Z');
* elsif (REBBUS='0' and CEBBUS='0') then
* DQ <=(others=>'Z');
* DATABUS <=DQ;
* else
* DQ <=(others=>'Z');
* DATABUS <=(others=>'Z');
* end if;
* end process;

But when a use Synthesis, i found this message:

*@W:"c:\project\dssss\fpga\dspprogv5\hdl\toptop.vhd":34:8:34:9|Found
*combinational loop during mapping
*24) instance DQ_pad[0] work.SDRAMDriverCore(behavioral)-DQ_pad[0],
output *net "DQ_in[0]" in work.SDRAMDriverCore(behavioral)
* input nets to instance:
* net "DATABUS_in[0]" in work.SDRAMDriverCore(behavioral)
* net "N_301_i" in work.SDRAMDriverCore(behavioral)

and this is for each line.

I understand message, but i don't know how to suppress this warning.
And make a good vhdl desciption.
When i check the logic circuit, a goot synthese can be seen.
What can i do to have not this warning ?
Best regards,
Animax.