Hi,
I'm grad student in a VLSI lab. I'm doing a long-time (days) measurement on a test digital chip using NI Dac system controled by labview. We observed that there will be voltage spikes from the oscilloscope due to the light/electrical device switching or static discharge around the test bench. These spikes may be induced by the EM field pulse, because the area formed by the wires matters. From the oscilloscope, we found that the peak-to-peak value can reach up to 10v for these spikes, which can easily toggle the input digital signal or the Vdd, and easily mess up the FFs inside the chip.
The attachment is the snapshot from oscilloscope of this kind of noise.
Not sure if you guys have had the same experience while doing the circuit test, and how did you prevent this?
Thank you very much.
I'm grad student in a VLSI lab. I'm doing a long-time (days) measurement on a test digital chip using NI Dac system controled by labview. We observed that there will be voltage spikes from the oscilloscope due to the light/electrical device switching or static discharge around the test bench. These spikes may be induced by the EM field pulse, because the area formed by the wires matters. From the oscilloscope, we found that the peak-to-peak value can reach up to 10v for these spikes, which can easily toggle the input digital signal or the Vdd, and easily mess up the FFs inside the chip.
The attachment is the snapshot from oscilloscope of this kind of noise.
Not sure if you guys have had the same experience while doing the circuit test, and how did you prevent this?
Thank you very much.
