Ben Bradley said:
I don't know specifics, but in general the thing with lower power
is you can pretty easily "design" with oversized components (good
powerfets sure are cheap thesedays) that can take the spikes generated
by a "just build the schematic and run with it" design. With higher
power there's not as much overhead with components (well maybe there
could be but it's cheaper to design right than use overrated
components) so you have to use proper layout and carefully controlled
switching times to reduce spike generation, and snubbers to lower the
levels of the spikes that still get generated.
IMO this is only done because the "designer" doesnt understand enough to be
able to tackle the design analytically. Although once you understand the
basic principles behind inductance you can design a minimal-inductance
system with no maths at all.
Read up on switching power supply design - it's very similar, in
fact a PWM H-bridge is just a specialized, variable-output swithmode
power supply. Linear Technology has some good stuff in their data
sheets and app notes, as do many others. Learn which way the big
switching currents go and use thick short traces for them (move
components around so that high-current traces are short), how to
reduce stray inductance, where to use snubbers.
See the current thread: "SMPS layout hints besides National
AN-1149?"
"Power Electronics" by Mohan, Undeland & Robbins (John Wiley) is pretty
good. I have the 1st edition but the 2nd edition has quite a bit more good
stuff.
If you really understand the statement "current flows in loops," understand
that inductance is proportional to physical loop area and know how to
calculate V=LdI/dt, then you have most of the tools you need. Add in the
ability to analyse an RLC circuit, and youre done.
A big IGBT might switch 500A in say 200ns giving dI/dt = 500/200ns =
2500A/us. 100nH of "stray" inductance gives a voltage spike of 250V. ouch.
And during an overcurrent fault, the IGBT current might rise to 5,000A so
the resulting inductive spike is a whopping 2,500V - kaBOOM (I have
personally worked on large drives where the overcurrent "desaturation"
circuit kicked in and blew the IGBT to bits every time during a
short-circuit, by turning it off nice and fast. doh
.
as you can see, 100nH stray inductance is enough to bugger a decent smps.
Tricks like parallel-plates for the DC bus with very small gaps (eg 10mil
nomex) are used to reduce interconnect inductance, paralleling many
electrolytics reduces the cap bank ESL, local low-ESL "bypass" caps (again
many in parallel) can often provide much lower ESL than the electrolytic cap
bank etc. Often the limiting factor is the internal inductance of the power
devices - an H series IGBT from powerex is around 30nH, the U series around
24nH, from memory. Semikron make devices with inductances on the order of
2nH (semitop) and a big device has around 12nH. These big devices can of
course be paralleled to make even bigger ones....you can buy 4kV/2kA
IGBTs....
Other than that, the big stuff is just like the small stuff. Skin depth at
50/60Hz is about 10mm, so that makes an upper limit on bus-bar thickness.
And at 1,000A 1mOhm dissipates 1kW.....so watch interconnects!
oh yeah, the fault currents are typically HUGE, you are invariably connected
to a VERY stiff supply. Poor discrimination in your choice of fusing can
lead to some spectacularly deadly results. Entire sections of inverters have
been known to disappear...
its kind of fun to design a power supply that is 95% efficient and has to
dissipate 50kW of losses....
Cheers
Terry
