[electronicsLearner77]

Is there any standard procedure for calculating interrupt latency? I mean to say can we estimate accurately the time it takes to go to the interrupt after the trigger. I am referring to dspic33ev family. I am finding the timing keeps varying and very difficult to design the system. Please advise.

 

[Amar Dhore]

Yes. You can accurately calculate by looking at Assembly code and then calculate the instruction cycles from the time interrupt triggers.

Time from Trigger into the ISR can vary only if there are higher priority interrupts are being triggered at the same time. Do you have multiple interrupts?

 

[dorke]

Generally there is no way to calculate the interrupt latency accurately.
The reasons are :

1.The interrupt priority structure is a non deterministic factor(unless you are talking about the top priority interrupt).

2.The code may contain periods in which interrupts are disabled.

3.Upon an interrupt execution ,the "current" executing instruction shall be ended first (may be variable length for CISC like machines) and than the "status"is saved to stack.

4.The only interrupt who's latency may be more or less accurately calculated is the NMI (non-maskable interrupt) only #3 above is a factor with the NMI.
If it's a RISC, single cycle, machine the resolution will be a single clock.