Logic family selection

[Sravanthi]

Yes, the fact that you cannot rely on an open TTL input to float to a high condition. It floats high by accident, not by design. It is a relatively high input impedance condition, and radiated noise can cause the input to transition. For any logic family at any time, never leave an input floating.

ak

Thank you for reply..
Then Pull up resistor is an acceptable solution for OR gate.
How to construct AND gate with those 2 requirements??
Help me in making this circuit.

 

[AnalogKid]

Here is what I think so far. Section A is the two input signals. Section B is a bare minimum approach. Section C is a more traditional approach. These are designed to drive a CMOS logic gate input. Note that both B and C end with a pull up resistor as indicated in previous posts. Depending on the voltage and current for the input signal, Section C might need resistors in series with the bases. Also, these circuits need to be tested with a 40 us pulse signal.

ak

 

[AnalogKid]

I have a requirement to the OR gate as open input(This may happen with some failure to the input eg like PCB track cut) ...

This is a strange requirement. How can this happen? Where is this pc board going to be located where its traces can be cut while in operation?

ak

 

[BobK]

This is a strange requirement. How can this happen? Where is this pc board going to be located where its traces can be cut while in operation?

ak

In a CNC machine?

 

[AnalogKid]

Pretty sure that doesn't matter, unless the control system is mounted to one end of the table...

ak

 

[Sravanthi]

This is a strange requirement. How can this happen? Where is this pc board going to be located where its traces can be cut while in operation?

ak

This may not happen.
Since I am doing FMEA(failure mode effect analysis) I have to consider all the failures.

 

[Sravanthi]

Here is what I think so far. Section A is the two input signals. Section B is a bare minimum approach. Section C is a more traditional approach. These are designed to drive a CMOS logic gate input. Note that both B and C end with a pull up resistor as indicated in previous posts. Depending on the voltage and current for the input signal, Section C might need resistors in series with the bases. Also, these circuits need to be tested with a 40 us pulse signal.

ak
View attachment 22872

Thank you for reply...
Here also requirement 2(mentioned in 7 th post) is not satisfied (The component, (eg. transistor or MOS) which takes input fails in short/open, output should goes to logic zero).
Consider Section B schematic.
If A input is logic 0 and B is logic 1 and D3 is failed in open then output is logic high,which is not as per requirement.
The similar problem exist in section C schematic,
If A=0 and B=1 and Q1 failed in short then output goes to high.
How to solve this

 

[AnalogKid]

This may not happen.
Since I am doing FMEA(failure mode effect analysis) I have to consider all the failures.

No, you don't. You have to consider all *reasonable* failures. The circuit might fail because it was hit by an asteroid, but I would not spend design time trying to account for this.

ak

 

[Sravanthi]

No, you don't. You have to consider all *reasonable* failures. The circuit might fail because it was hit by an asteroid, but I would not spend design time trying to account for this.

ak

Open input to the AND can be solved with pull down resistor. Even though its not reasonable it has to be considered.
Transistor or diode failure in short and open are reasonable failures. But this problem is not solved with the given schematic.
So please consider this problem and give me a solution.
Thank you...

 

[AnalogKid]

Automatic handling of all possible error conditions is not possible.

An absolute solution is not possible, because both failure logic states also are valid logic states for normal operation. If the input is a continuous waveform with a minimum frequency, you can add a monitor circuit to detect if it has stopped in either logic state. But that is a large increase in circuits, and now you have to worry about a device failure in the monitor circuit giving you a false alarm, or missing a valid alarm.

You need to put firm boundaries on your requirements, because automatic handling of all possible error conditions is not possible.

ak

 

[Sravanthi]

Automatic handling of all possible error conditions is not possible.

An absolute solution is not possible, because both failure logic states also are valid logic states for normal operation. If the input is a continuous waveform with a minimum frequency, you can add a monitor circuit to detect if it has stopped in either logic state. But that is a large increase in circuits, and now you have to worry about a device failure in the monitor circuit giving you a false alarm, or missing a valid alarm.

You need to put firm boundaries on your requirements, because automatic handling of all possible error conditions is not possible.

ak

I agree with your point,that addition of extra circuitry for monitoring will make circuit complex.
My aim is not to add extra circuit for monitoring and giving indication that it has failed. When ever one of the transistor or diode fails it has to drive AND gate output to zero. Does this not possible with simple additional components in series or parallel to diode or transistor.
Thank you...