I'm trying to design a Manchester Encoder using a PISO shift register and an XOR gate. I ran into a couple problems.
1. Timing: I need to synchronize the shift register output with the clock (clocking it) i.e. I need to delay the clock (running at 100 kHz) by td (the IC’s time delay) which about 16ns.
2. Multiple edges: I need to eliminate the edges caused by the simultaneous switching of logic states of the gate (XOR) inputs (i.e. NRZ/binary data and clock signal respectively)
Help in this regard would be highly appreciated. An alternative design is also welcome!!!
Email me at: [email protected]
1. Timing: I need to synchronize the shift register output with the clock (clocking it) i.e. I need to delay the clock (running at 100 kHz) by td (the IC’s time delay) which about 16ns.
2. Multiple edges: I need to eliminate the edges caused by the simultaneous switching of logic states of the gate (XOR) inputs (i.e. NRZ/binary data and clock signal respectively)
Help in this regard would be highly appreciated. An alternative design is also welcome!!!
Email me at: [email protected]
