mosfet switching time vs temperature

[Jamie Morken]

Hi,

For an n-channel mosfet how does increasing junction temperature effect
the switching time? I was wondering about paralleling mosfets, if one
fet switches a bit faster than the others and heats up, will its
switching time increase or decrease. I am hoping for increase!

cheers,
Jamie

 

[Tim Williams]

Capacitance probably doesn't change. Threshold will though. The hottest
will switch on sooner due to reduced Vgs(th).

Just how slowly are you switching them that you're concerned about thermal
effects in parallel? 10us+? Doesn't matter, switching mode FETs parallel
good anyway.

And don't you mean decrease, anyway?

Tim

 

[Jamie Morken]

Capacitance probably doesn't change. Threshold will though. The hottest
will switch on sooner due to reduced Vgs(th).

Just how slowly are you switching them that you're concerned about thermal
effects in parallel? 10us+? Doesn't matter, switching mode FETs parallel
good anyway.

And don't you mean decrease, anyway?

Tim

Hi,

Nope I meant increase. The fastest FET will absorb more of the
switching losses than the slower FETs in parallel with it, and to a
lesser extent during the extra few nanoseconds it might be on, it is
absorbing all the losses that would otherwise be spread equally over the
fets once they are all turned on. For say 5 parallel fets, this could
become significant if the same FET is always turning on first. From
what you said about V(gs) decreasing with temperature, it seems like it
could be a problem for parallel FETs. It would be good to use a delay
to allow one FET to turn on faster than the others, and for each switch
transition, change the FET that turns on first so that the switching
losses are evenly distributed. That circuit would require individual
gate drivers per FET instead of the simpler parallel resistors and
single gate drive.

cheers,
Jamie

 

[Jamie Morken]

The faster FET has lower switching loss, but has marginally more (a
few nS' worth) conduction loss, right?

Hi,

For the parallel FETs, the faster FET has more switching loss than the
slower switching ones, since the other FETs may switch for free, due to
zero voltage switching (ZVS) once the first FET has turned on the drain
voltage will be near 0V (for n channel lowside FET switching
applications etc)

cheers,
Jamie

 

[legg]

Hi,

Nope I meant increase. The fastest FET will absorb more of the
switching losses than the slower FETs in parallel with it, and to a
lesser extent during the extra few nanoseconds it might be on, it is
absorbing all the losses that would otherwise be spread equally over the
fets once they are all turned on. For say 5 parallel fets, this could
become significant if the same FET is always turning on first. From
what you said about V(gs) decreasing with temperature, it seems like it
could be a problem for parallel FETs. It would be good to use a delay
to allow one FET to turn on faster than the others, and for each switch
transition, change the FET that turns on first so that the switching
losses are evenly distributed. That circuit would require individual
gate drivers per FET instead of the simpler parallel resistors and
single gate drive.

cheers,
Jamie

For fets driving the same drain node, the drain of the part with the
lowest threshold voltage will drive the Cdg of all paralleled parts -
potentially acting against their enhancement.

If the drain voltage doesn't fall immediately - due to rectifier
stored charge or other factors, all gates will likely be enhanced by
the drive before the drain voltage dv/dt becomes signifigant.

RL

 

[Jamie Morken]

You mean switches slower, thereby having a longer transition time,
resulting in more power dissipation?

Hi,

Switching faster is good overall, ie. all the parallel FETs switching at
an average time of 10ns is better than an average time of 100ns, but
once they all average 10ns, it may be better that the fastest FET in the
group, ie. one with a 9ns switching time, and thus absorbing more of the
switching losses perhaps, would switch slower once it heated up.

cheers,
Jamie

 

[Jamie Morken]

For fets driving the same drain node, the drain of the part with the
lowest threshold voltage will drive the Cdg of all paralleled parts -
potentially acting against their enhancement.

If the drain voltage doesn't fall immediately - due to rectifier
stored charge or other factors, all gates will likely be enhanced by
the drive before the drain voltage dv/dt becomes signifigant.

RL

That went a mile over my head

cheers,
Jamie

 

[Tim Williams]

Mosfets get slower when they get hotter. You can see this in common
cmos logic... HC, FPGAs, whetever: prop delay increases with
temperature. For HC, it's around 2% per degree C. FPGAs are a little
better, typically maybe 1%, possibly because a lot of the delay is
caused by routing and not just fets.

That's probably due to Rds(on) increasing. Low voltage FETs don't
increase much, you can buy 20-30Vds(max) FETs that are <1.3 Rds(25) at
150C. That's a better tempco than copper. FETs in logic chips probably
have the same tempco.

Curiously, the tempco increases dramatically in just a few tens of
Vds(max). 50-60V FETs are ~1.8 and 100V+ are about double. 1000V FETs
are about 2.5x. That high voltage drift region sure gets long quickly.

Tim