PLL synthesizer: Influence frequency resolution on loop bandwidth

[Foxbox]

Hi all,

considering a PLL synthesizer like here:

When you want a high frequency resolution, you choose R high. According to my notes taken during class, increasing R requires decreasing the bandwidth of the loop filter. I also noted this is because of "divider delay"...

It's a long time ago and I have really no idea where this comes from.

Could you give me some pointers?

thanks in advance,
Foxbox

 

[duke37]

Not my area but this will not stop me!

R gives the reference frequency and I do not see that it matters where this comes from.

N is in the loop and so any delay here will be important.