SDIO Debugging Help

[jdhar]

I am having a seriously difficult time resolving an issue with a
custom IC and the SDIO device interface on it.

The setup:

Device IC (with SDIO interface) <---> 8-pin male 100 mil header on PCB
<----> Short cable <---> SDIO Finger PCB with 8-pin male 100 mil
header <----> Host system with SDIO slot

So the device IC resides on a PCB with an 8-pin header. The SDIO
finger PCB is a small PCB that is in the shape of a SDIO card, and it
has a matching 8-pin header. This plugs into the SDIO host.

The problem:

Spurious interrupts are generated/detected in the system, and CRC
errors occur from time to time.

Details:

The first problem is narrowing down whether this is a Signal-
integrity (SI) issue, or a RTL/IP issue. Right now, the symptoms are
pointing to an SI issue, however, I can't seem to accept that an SDIO
interface running at 10 MHz would be prone to SI. I know that SI is
more related to edge rates instead of frequency, but still at 10 MHz,
the system should be relatively forgiving. Some interesting notes:

- Using a regular IDC ribbon cable yields the worst results; ie, more
frequent CRC errors and sometimes the setup dies immediately
- Using Coax cable on all signals (with grounds tied together on both
ends) definitely improves things
- Soldering the Edge-finger board directly to the Device Board also
improves things, but still not completely resolved
- Increasing the length of the Clock trace to 70+" with the rest of
the signals at ~3" improves the same way coax does. This is what
yields me to believe it may not be purely an SI issue.
- Adding series resistance or small shunt capacitance doesn't yield
any noticeable results
- Clipping a regular passive probe onto the clock line improves things

I have probed all of the lines with active probes (since passive
probes change the results), and there is no noticeable quality issues.
I am probing at the header on the Device side, which is about half way
between the 'chain'.

Any suggestions on where to look here? I'm at wits end!

 

[MK]

I am having a seriously difficult time resolving an issue with a
custom IC and the SDIO device interface on it.

The setup:

Device IC (with SDIO interface) <---> 8-pin male 100 mil header on PCB
<----> Short cable <---> SDIO Finger PCB with 8-pin male 100 mil
header <----> Host system with SDIO slot

So the device IC resides on a PCB with an 8-pin header. The SDIO
finger PCB is a small PCB that is in the shape of a SDIO card, and it
has a matching 8-pin header. This plugs into the SDIO host.

The problem:

Spurious interrupts are generated/detected in the system, and CRC
errors occur from time to time.

Details:

The first problem is narrowing down whether this is a Signal-
integrity (SI) issue, or a RTL/IP issue. Right now, the symptoms are
pointing to an SI issue, however, I can't seem to accept that an SDIO
interface running at 10 MHz would be prone to SI. I know that SI is
more related to edge rates instead of frequency, but still at 10 MHz,
the system should be relatively forgiving. Some interesting notes:

- Using a regular IDC ribbon cable yields the worst results; ie, more
frequent CRC errors and sometimes the setup dies immediately
- Using Coax cable on all signals (with grounds tied together on both
ends) definitely improves things
- Soldering the Edge-finger board directly to the Device Board also
improves things, but still not completely resolved
- Increasing the length of the Clock trace to 70+" with the rest of
the signals at ~3" improves the same way coax does. This is what
yields me to believe it may not be purely an SI issue.
- Adding series resistance or small shunt capacitance doesn't yield
any noticeable results
- Clipping a regular passive probe onto the clock line improves things

I have probed all of the lines with active probes (since passive
probes change the results), and there is no noticeable quality issues.
I am probing at the header on the Device side, which is about half way
between the 'chain'.

Any suggestions on where to look here? I'm at wits end!

This may be way off line but I'll offer it up:

If either of your devices is using a software configured SPI port for the
SDIO interface it may be set up to transfer data on the wrong clock edge.
Amazingly this can often work due to slight timing skew between clock and
data but of course the resulting interface is very sensitive to tiny SI
issues.
Have seen product in the field with occasional (obviously only fitted to the
ones that did not work) tiny capacitor added to the data line to make SPI IO
work rather than fix the code !!!

Good luck

Michael Kellett

www.mkesc.co.uk

 

[[email protected]]

Have seen product in the field with occasional (obviously only fitted to the

ones that did not work) tiny capacitor added to the data line to make SPI IO
work rather than fix the code !!!

That's gross..
Btw, All SDIO transfers are protected by CRC ..?

 

[[email protected]]

Spurious interrupts are generated/detected in the system, and CRC

errors occur from time to time.

..
..

Check connection, and.. check that the SDIO card is properly decoupled.
Is the sdio shielded from rf?

- Using a regular IDC ribbon cable yields the worst results; ie, more
frequent CRC errors and sometimes the setup dies immediately
- Using Coax cable on all signals (with grounds tied together on both
ends) definitely improves things

Ground shall only be grounded at one end asfair.
And cables with every other conductor at ground may help too (like UDMA cable).

- Increasing the length of the Clock trace to 70+" with the rest of
the signals at ~3" improves the same way coax does. This is what
yields me to believe it may not be purely an SI issue.

Could be inverted signaling as the other poster indicated.
But another cause could be that the clock is activated at the same time as
the data is put on the line. Thus relying on chance for proper reception.

- Clipping a regular passive probe onto the clock line improves things

More capacitance -> Longer slewrate.