Kevin Weddle
- Feb 23, 2004
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I know that you may not get what you want in a shift register. I bought a shift register and the first bit I put into it jumped to the output. Shift registers make good delay devices and are chiefly used for storage. Whenever you have bits of information you must clock the data so that the device knows where in time the information is.
surajbarkale
- Aug 5, 2004
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Shift registers are good dividers too. google "shift register theory" this and read till you get tired
Adam,
Here is a basic diagram (below) of a 4 bit shift register made from 4 D flip flops connected in series. The parallel output is displayed at D,C,B,A.
To understand the logic of this circuit, assume the output at Q of each flip flop is at logic 0. When a clock pulse is applied to the SHIFT line, the logic level at the D input of each flip flop is loaded into the corresponding flip flop. For example, if all Q outputs are initially at logic 0,the status of the 4 outputs, (0000) will not be changed after the arrival of the clock pulse. Now, if a logic 1 is applied to the serial input, a logic 1 will be loaded into the first flip flop when the next clock pulse arrives. The 4 bit output nibble appearing at the parallel output will then be 1000 with a logic 1 appearing at parallel output "D". If the logic level at the serial input is then changed to logic 0, the logic 1 will move one position to the right at the next clock cycle. The 4 bit nibble stored in the register will then be 0100. The movement to the right of the logic 1 will continue with each clock cycle. The nibble changes to a 0010, and then to a 0001. This is provided that logic 0's are loaded into the register after our initial logic 1 which we are watching go through the register. At the fifth clock cycle, the logic 1 is pushed completely out of the register. Provided no other logic 1's were pushed into the register, the nibble will once again be 0000.
Four significant things have happened here in 5 clock cycles:
1. A logic 1 applied at the SERIAL INPUT appeared at the SERIAL output after the arrival of 4 more clock cycles. Thus the register acted as a digital delay line.
2. The logic 1 appeared in sequence at 4 of the parallel outputs. This action was controlled by the clock cycles. Thus, the outputs of the register can be used to sequentially control other devices connected to A through D as a pattern sent to the serial input.
3. The bit pattern appearing at the 4 parallel outputs can be considered a binary word. As the bits moved from left to right, the magnitude of the word was halved at each clock cycle.
Note: In binary, 1000 = 8, 0100 = 4, 0010 = 2, and 0001 = 1. Thus, the shift register has performed a numeric divide by two operation with each clock cycle.
4. Between clock pulses, the register has acted as a conventional data storage register. The register stored the data without changing it. The data was always available at the parallel outputs.
Hope it is helpful in your project.
MP
View attachment 36239
Here is a basic diagram (below) of a 4 bit shift register made from 4 D flip flops connected in series. The parallel output is displayed at D,C,B,A.
To understand the logic of this circuit, assume the output at Q of each flip flop is at logic 0. When a clock pulse is applied to the SHIFT line, the logic level at the D input of each flip flop is loaded into the corresponding flip flop. For example, if all Q outputs are initially at logic 0,the status of the 4 outputs, (0000) will not be changed after the arrival of the clock pulse. Now, if a logic 1 is applied to the serial input, a logic 1 will be loaded into the first flip flop when the next clock pulse arrives. The 4 bit output nibble appearing at the parallel output will then be 1000 with a logic 1 appearing at parallel output "D". If the logic level at the serial input is then changed to logic 0, the logic 1 will move one position to the right at the next clock cycle. The 4 bit nibble stored in the register will then be 0100. The movement to the right of the logic 1 will continue with each clock cycle. The nibble changes to a 0010, and then to a 0001. This is provided that logic 0's are loaded into the register after our initial logic 1 which we are watching go through the register. At the fifth clock cycle, the logic 1 is pushed completely out of the register. Provided no other logic 1's were pushed into the register, the nibble will once again be 0000.
Four significant things have happened here in 5 clock cycles:
1. A logic 1 applied at the SERIAL INPUT appeared at the SERIAL output after the arrival of 4 more clock cycles. Thus the register acted as a digital delay line.
2. The logic 1 appeared in sequence at 4 of the parallel outputs. This action was controlled by the clock cycles. Thus, the outputs of the register can be used to sequentially control other devices connected to A through D as a pattern sent to the serial input.
3. The bit pattern appearing at the 4 parallel outputs can be considered a binary word. As the bits moved from left to right, the magnitude of the word was halved at each clock cycle.
Note: In binary, 1000 = 8, 0100 = 4, 0010 = 2, and 0001 = 1. Thus, the shift register has performed a numeric divide by two operation with each clock cycle.
4. Between clock pulses, the register has acted as a conventional data storage register. The register stored the data without changing it. The data was always available at the parallel outputs.
Hope it is helpful in your project.
MP
View attachment 36239
Last edited by a moderator:
shekhar_dandya
- Jun 18, 2004
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Hi Everyone,
This was the question asked to one of my collegue in interview:
Data is comming on a serial line at 1Mbps.I want to delay this data by 1 sec .How do I acomplish it?
Using shift register with a 1Mhz clock and 1 million+1 D flip flops.
This is my answer.
Is there any more elegant solution?
This was the question asked to one of my collegue in interview:
Data is comming on a serial line at 1Mbps.I want to delay this data by 1 sec .How do I acomplish it?
Using shift register with a 1Mhz clock and 1 million+1 D flip flops.
This is my answer.
Is there any more elegant solution?
shekhar_dandya
- Jun 18, 2004
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Hi Enigma one,
FIFO of what size?
-Shekhar
FIFO of what size?
-Shekhar
shekhar_dandya
- Jun 18, 2004
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Hi enigma one,
So this again means u require 1 million locations to store
So this again means u require 1 million locations to store
Kevin Weddle
- Feb 23, 2004
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Shekar, to get that much delay you might as well store it in RAM and retrieve it pending a real time clock.
There are delay chips and sample-hold chips on the market that can be used to achieve what you are trying to do. Also, the music industry is pretty well accomplished in delay techniques to get echo. Some of these devices will give you as much as 4 seconds of delay. You might want to research that area. Just curious: Why would you want to delay a digital transmission?
MP
MP
Kevin Weddle
- Feb 23, 2004
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Shekhar, the rate the data enters the device will affect how much storage you need. If you start retrieving the data as soon as 1 second is up, you will have compiled a whole mess of data. But that data will leave consecutively with the first data put into the device. So if you clock the data in at 4MHZ, you will have 1 bit per cycle and will have to store 4Mbits.
shekhar_dandya
- Jun 18, 2004
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Hi all,
Quote from MP:
Thanks
-Shekhar
Quote from MP:
Well,this was just a question asked to test my friend in an interview.
Thanks
-Shekhar
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