Simulation in DipTrace 5.0

[RenoX]

I have created a schematic, see the attached screenshot. Now I am trying to simulate how it works in a digital SPICE simulator (built-in DipTrace 5.0 beta).



In general, it works almost reasonably. But there are strange signal distortions on some outputs of U3 on each falling edge of the clock coming to the input of decade counter U5. I have shown the problem with red marks.



What I am doing wrong? Is it a simulator issue or the schematic is incorrect?

 

[Harald Kapp]

What I am doing wrong? Is it a simulator issue or the schematic is incorrect?

Nothing wrong here.
Have a look at U5, Qa...Qd. You will find that these glitches occur when two outputs of U5 change simultaneously. The decoding logic in U3 detects a wrong intermediate state which leads to the short glitch you see in the waveform diagram.

The outputs of U5 change with the rising edge of the clock signal. To suppress the glitches, you can for example add a register to the output of U3 and control the latch input (or clock input) of the register by the inverse of the clock. Such that the additional latch is activated when the clock goes low. Then the glitches, which occur with the rising edge of the clock, are ignored.

 

[RenoX]

Thank you for your help. Bests regards.