what I know is
whatever may be the configuration (ce cb or cc)
In active region
Base emitter junction is forward biased and collector base junction is reverse biased
In cutoff region
Both the junctions are reverse biased
In saturation region
Both the junctions are forward biased
lets now divert our attention towards the working of the transistor in the saturation region
yesterday I was reading a book named electronic devices and circuits by david a bell .(page number 159 5th edition )
in that he wrote that
“if Vce went down to exactly zero volts , the collector base junction would become forward biased by 0.7v .in this case the collector base barrier voltage would be overcome and charge carriers from the emitter would be repelled from the collector base junction “and due to some things which were explained later in the book it doesnot happen so some collector current will flow so the voltage will Vce(sat)=0.2Vthis means the collector current should decrease as cb becomes forward biased
let us now see CB configuration output characteristics of a npn transistor
http://www.nptel.ac.in/courses/117107095/lecturers/lecture_11/images/fig7.jpg (pls see this link for characteristics)
as we can see sir if we decrease the voltage Vcb below zero we know that collector base junction will start to become forward biased (if it reaches 0.7v then it will become CB junction will become forward biased ) . So as the cb junction is starting to become forward biased (i.e,. as Vcb<0 ) then collector current is starting to decrease .
so as said above it is happening . So its fair.
But my question is that it is not happening in the ce configuration
when Vce reaches Vce(sat) maximum current is passing through the collector . How come this can happen ? How come transistor allows maximum current in the saturation region.
the reason I am asking this is, in saturation region the collector base junction which is forward biased should repel all the charge carriers from the emitter . but still we all get maximum current flowing through the transistor when it is in saturation mode (applied that it is operating in the ce configuration )
how come max current flow in ce but very least current flow in the cb configuration when the transistor is taken to their saturation region ?
whatever may be the configuration (ce cb or cc)
In active region
Base emitter junction is forward biased and collector base junction is reverse biased
In cutoff region
Both the junctions are reverse biased
In saturation region
Both the junctions are forward biased
lets now divert our attention towards the working of the transistor in the saturation region
yesterday I was reading a book named electronic devices and circuits by david a bell .(page number 159 5th edition )
in that he wrote that
“if Vce went down to exactly zero volts , the collector base junction would become forward biased by 0.7v .in this case the collector base barrier voltage would be overcome and charge carriers from the emitter would be repelled from the collector base junction “and due to some things which were explained later in the book it doesnot happen so some collector current will flow so the voltage will Vce(sat)=0.2Vthis means the collector current should decrease as cb becomes forward biased
let us now see CB configuration output characteristics of a npn transistor
http://www.nptel.ac.in/courses/117107095/lecturers/lecture_11/images/fig7.jpg (pls see this link for characteristics)
as we can see sir if we decrease the voltage Vcb below zero we know that collector base junction will start to become forward biased (if it reaches 0.7v then it will become CB junction will become forward biased ) . So as the cb junction is starting to become forward biased (i.e,. as Vcb<0 ) then collector current is starting to decrease .
so as said above it is happening . So its fair.
But my question is that it is not happening in the ce configuration
when Vce reaches Vce(sat) maximum current is passing through the collector . How come this can happen ? How come transistor allows maximum current in the saturation region.
the reason I am asking this is, in saturation region the collector base junction which is forward biased should repel all the charge carriers from the emitter . but still we all get maximum current flowing through the transistor when it is in saturation mode (applied that it is operating in the ce configuration )
how come max current flow in ce but very least current flow in the cb configuration when the transistor is taken to their saturation region ?
