4093 and 4070

[ilia]

hi, I'm using these two components on my circuit, they both have 4 gates on one 14 pin chip, but I don't need the whole functionality. Can I just leave the unneeded pins not connected? or must I connect them to Vcc/ground ?
The datasheet says nothing about this issue...

Thank you!

 

[KrisBlueNZ]

You must connect them (Edit: You must connect ALL INPUTS) to something, otherwise they will float and pick up noise. This can cause increased current consumption (because the MOSFETs inside the gate operate in their "linear region" where both can conduct simultaneously, causing a current path across the supply rails) and sometimes other misbehaviour.

You can connect unused inputs to VDD, VSS, or any other signal point in the circuit that will be at a clearly defined logic level, such as the output of any other gate.

You know about decoupling capacitors? Each IC should have a small-value capacitor, typically 0.1 µF, ceramic, connected between its VDD and VSS pins as closely and directly as possible. This is needed because when CMOS gates switch, there is a brief time when the MOSFETs inside the gate conduct simultaneously, as I mentioned above. This causes a "shoot-though" current burst, which can pull the supply voltage down briefly and cause other gates or other parts of the circuit to misbehave. Each decoupling capacitor acts as a local reservoir that supplies the little bursts of current and keeps the supply rails from dipping.

 

[ilia]

You must connect them to something, otherwise they will float and pick up noise. This can cause increased current consumption (because the MOSFETs inside the gate operate in their "linear region" where both can conduct simultaneously, causing a current path across the supply rails) and sometimes other misbehaviour.

You can connect unused inputs to VDD, VSS, or any other signal point in the circuit that will be at a clearly defined logic level, such as the output of any other gate.

You know about decoupling capacitors? Each IC should have a small-value capacitor, typically 0.1 µF, ceramic, connected between its VDD and VSS pins as closely and directly as possible. This is needed because when CMOS gates switch, there is a brief time when the MOSFETs inside the gate conduct simultaneously, as I mentioned above. This causes a "shoot-though" current burst, which can pull the supply voltage down briefly and cause other gates or other parts of the circuit to misbehave. Each decoupling capacitor acts as a local reservoir that supplies the little bursts of current and keeps the supply rails from dipping.

Wow thanks alot. I did not know these things. thank you!

 

[(*steve*)]

Specifically, you must connect the *INPUTS* to a valid logic level. Generally you can connect them to whatever is the most convenient, gnd, Vcc, or even another logic level from somewhere else.

However the *OUTPUTS* should not be tied to anything else. Most frequently these are left open.

This is exactly what Kris has said, I am just emphasizing that the outputs shouldn't be tied to ground (for example).

 

[ilia]

Specifically, you must connect the *INPUTS* to a valid logic level. Generally you can connect them to whatever is the most convenient, gnd, Vcc, or even another logic level from somewhere else.

However the *OUTPUTS* should not be tied to anything else. Most frequently these are left open.

This is exactly what Kris has said, I am just emphasizing that the outputs shouldn't be tied to ground (for example).

excellent. that was going to be my next question.

 

[ilia]

Each IC should have a small-value capacitor, typically 0.1 µF, ceramic, connected between its VDD and VSS pins as closely and directly as possible.

Actually I have two more questions:
1. Does the capacitor have to be ceramic? I assume it's because it needs to be non polar?
2. If I have 3 IC on my circuits each connected to the same rails for VSS and VDD. If I connect a 0.1uF capacitor between the VSS and VDD of each chip. Isn't it the same as connecting 0.3uF between the two rails no matter where?

 

[(*steve*)]

1. Does the capacitor have to be ceramic? I assume it's because it needs to be non polar?

No, but they're usual because they're small and cheap.

They're also typically of low inductance and the answer to your next question will indicate why that is important.

2. If I have 3 IC on my circuits each connected to the same rails for VSS and VDD. If I connect a 0.1uF capacitor between the VSS and VDD of each chip. Isn't it the same as connecting 0.3uF between the two rails no matter where?

Not quite.

The capacitance placed near the pins of the IC reduces the effect of inductance present in the wiring. Because digital signals switch very rapidly, the frequency at which current demands change can be very high (faster even than the fastest speed the logic is specified for). At these frequencies the wiring inductance is sufficient that it really does make a difference how close you place the capacitor.

For through-hole components it is not unusual to see them soldered directly onto the pins of the IC on the underside of the board.

The closer you put them the less weirdness with odd ground and supply voltages you'll get. In the worst case, this weirdness can result in one logic level being seen as the other!