A 16-bit-wide instruction opcode can specify 65536 different instructions. No processor needs that many distinctly different instructions, so the instruction word is generally divided into bitfields.
For example, there might be a single instruction to copy the contents of one register to another register, on a processor with 32 general purpose registers. This instruction might be encoded like this:
Code:
c c c c c c s s s s s d d d d d
----------- --------- ---------
--opcode--- -source-- destination
i.e. a six-bit opcode that identifies the instruction as a register-to-register copy, with a five-bit field to specify the source register and a five-bit field to specify the destination register, for a total instruction word width of 16 bits.
Other instructions might be encoded differently. For example, there might be instructions to set or clear one specific bit in any register, which might be encoded like this:
Code:
c c c c c c a b b b b r r r r r
----------- - ------- ---------
--opcode--- a --bit-- register
This category of instruction needs a four-bit bit number (assuming registers are 16 bits wide), and a 5-bit register number. The action to be performed on the specified bit in the specified register- i.e. whether the bit is to be set or cleared - can be specified in another bit which I've called 'a'. That's ten bits, leaving (again) six bits for the opcode part of the instruction word.
The example signals you have appear to be control signals generated by the processor core for communication with external devices such as RAM or I/O space. These are generated by the instruction decoder, which takes the instruction word and interprets it. The instruction decoder knows what each opcode needs to do, and generates the right control signals in the right order so that the processor core performs the requested operation.
For example, for a register-to-register data copy, the instruction decoder recognises the top six bits of the instruction as a register-to-register data copy. It takes the 5-bit source register specification from the instruction word and puts it on the internal register address bus, then performs a read access of that memory space, to get the contents of that register. It stores the data in an internal holding register. Then it takes the 5-bit destination register specification from the instruction word and puts it on the internal register address bus, then perform a write to that memory space, with the holding register providing the data to be written. Once those two steps are up, it is ready to load and execute the next instruction.
The steps that are required in order to execute the instruction are encoded in a "microcode ROM" that is indexed by the opcode, and tells the instruction decoder what sequence of internal operations it needs to perform in order to execute the current instruction. These internal operations are performed by controlling the signals you listed - ram_rd_sel, ram_wr_sel, src_sel1, and so on.
This describes a fairly simple CPU. Real world CPUs, especially powerful and/or fast CPUs, use tricks to make the execution of instructions much quicker and more complicated. But a simple device like the original 8051 will just do it step-by-step according to the information stored in the microcode.
I hope this explains the missing link between instruction words and control signals.
