FET question

[HANKMARS]

I have forgotten, or perhaps have never known, the function of the zener diode connecting the source to the drain, internal within a FET. Is the zener inherent of the fabrication of the device or is it engineered and added? I suspect one function may be to keep current carriers from traveling out of the gate region. Will you enlighten me some on this matter? The photo file is of an IRF4905 P type enhancement mode FET that I'm using in a current project.

 

[bertus]

Hello,

The diode is part of the construction.
Read this wiki page and look for the body diode:
https://en.wikipedia.org/wiki/Power_MOSFET

Bertus

 

[HANKMARS]

Hello,

The diode is part of the construction.
Read this wiki page and look for the body diode:
https://en.wikipedia.org/wiki/Power_MOSFET

Bertus

Interesting article. Thank you. I downloaded as PDF. Interesting note is that PMOS device will have 3 times the Source to Drain resistance as an NMOSFET. I am thinking I may well modify my project design to accomodate an N type FET for power out stage since I am probably wasting battery power by creating heat with resistive load of P type FET.

 

[bertus]

Hello,

Most info and tutorials are related to the N-mosfets.
I have attached three of those documents.

Bristolwatch has a tutorial page that uses P-mosfets:
http://www.bristolwatch.com/ele/tr1.htm

I have also added a list of P-mosfets in the PDF.
(XLS and ODS , the spreadsheet formats, are not supported by the site).
You can use an PDF reader to zoom in on the page.
As you can see most modern mosfets are made in SMD formats.

Bertus

 

[HANKMARS]

Hello,

Most info and tutorials are related to the N-mosfets.
I have attached three of those documents.

Bristolwatch has a tutorial page that uses P-mosfets:
http://www.bristolwatch.com/ele/tr1.htm

I have also added a list of P-mosfets in the PDF.
(XLS and ODS , the spreadsheet formats, are not supported by the site).
You can use an PDF reader to zoom in on the page.
As you can see most modern mosfets are made in SMD formats.

Bertus

Thank you.

 

[Harald Kapp]

Interesting note is that PMOS device will have 3 times the Source to Drain resistance as an NMOSFET.

Not necessarily. A p-channel is less conductive (higher resistance) than an n-channel given the same dimensions. This is due to the lower conductivity of the material. However, this can be compensated by using a wider channel. Therefore you can buy p-channel mosfets with low R_DSon as well. They are usually a bit more expensive, though.
P-channel mosfets are well suited to control the positive rail (high-side switches) with low effort for the control signal (to the gate). N-channel mosfets in this application require special drive circuits that are capable to generate control signals to the gate in excess of the positive supply rail.
It is a matter of economy whether you buy a more expensive P-channel mosfet or a less expensive n-channel mosfet plus a gate drive circuit.

I am probably wasting battery power by creating heat with resistive load of P type FET.

No you don't. On the contrary, increasing the resistance will lower the overall power dissipation. What happens is that less of the power is available to the load as more of it is dissipated within the mosfet.

 

[HANKMARS]

Not necessarily. A p-channel is less conductive (higher resistance) than an n-channel given the same dimensions. This is due to the lower conductivity of the material. However, this can be compensated by using a wider channel. Therefore you can buy p-channel mosfets with low R_DSon as well. They are usually a bit more expensive, though.
P-channel mosfets are well suited to control the positive rail (high-side switches) with low effort for the control signal (to the gate). N-channel mosfets in this application require special drive circuits that are capable to generate control signals to the gate in excess of the positive supply rail.
It is a matter of economy whether you buy a more expensive P-channel mosfet or a less expensive n-channel mosfet plus a gate drive circuit.


No you don't. On the contrary, increasing the resistance will lower the overall power dissipation. What happens is that less of the power is available to the load as more of it is dissipated within the mosfet.

I think the Wiki article mentioned that since the conducting channel of a PMOS device is doped with a P type substance, holes, as opposed to electrons, will be the majority current carrier. The explanation was that holes do not have the mobility of electrons. I honestly do not know if this is an analogy or an accurate statement in regard to physics.

 

[Harald Kapp]

The physical explanation is correct. less mobility results in a higher resistivity here.

As an analogy: if you feed a liquid through a tube, the amount of liquid per unit of time (current) depends on the pressure (voltage), the tube diameter (resistance) and the viscosity of the liquid (majority carrier mobility).
If the liquid has low viscosity (e.g. water), a tube with a small diameter can transport lots of liquid at a given pressure. If on the other hand the liquid has high viscosity (e.g. honey), you need higher pressure or a wider tube to transport the same amount of liquid per unit of time. With given pressure (voltage), given viscosity (carrier mobility) and given amount of fluid per unit of time (current) but different viscosity, the only option is changing the diameter of the tube (aka width of the mosfet's channel) to achieve equal behavior.