JK Flip-Flop Toggles Twice from One Button Press

[eva_402]

Hi everyone,
I’m using a JK flip-flop for a simple state control circuit. Pressing the push button should toggle once, but sometimes the output changes twice or returns to the previous state.

The button has only a resistor and capacitor debounce network.

Questions:

1. Is the issue likely incomplete debouncing or clock edge sensitivity?
2. Would a Schmitt trigger between the button and clock input solve it properly?
3. On the PCB, should manual input traces be protected from nearby switching lines?

 

[Delta Prime]

I’m using a JK flip-flop for a simple state control circuit.

Could you show us a schematic of your circuit, please?

 

[Harald Kapp]

1. very much likely insufficient debouncing
2. possibly, but not necessarily
3. definitely

Here's a comprehensive text on debouncing.

 

[danadak]

RC approaches, without using a Schmidt trigger gate or comparator with hysteresis can
generate problems due to excessive rise and fall times associated with the C charging.

And hanging a large C off a cmos input pin can cause potential damage to cmos input
structure during supply collapse on turn off. Not advised, or add a series R between cap
and gate input to limit current thru input structure parasitic diodes and or ESD protection
circuitry.

https://toshiba.semicon-storage.com/info/application_note_en_20210131_AKX00111.pdf?did=63525

https://www.ti.com/lit/an/scba004e/scba004e.pdf?ts=1777226706625

https://www.ti.com/lit/ab/scea094/scea094.pdf?ts=1777268236060

And of course one can always do it with code :



The above bounces the button in and out before target code gets executed. Easily modified to just
+ edge needed to execute target code.

Classic

 

[Harald Kapp]

And of course one can always do it with code :

How would you apply the code to a JK-FF as stated in post #1?

 

[danadak]

Code eliminate need for J-K possibly, without schematic we need more complete
description. Is OP toggling J-K with button or sampling button with J-K and / or
using it as part of his state machine.....more info needed.

@OP

1. Is the issue likely incomplete debouncing or clock edge sensitivity?
2. Would a Schmitt trigger between the button and clock input solve it properly?
3. On the PCB, should manual input traces be protected from nearby switching lines?

I would say incomplete debouncing. Certainly schmidt could help if you need
JK for other circuit uses. Is it just there for button state ? PCB, if inputs are driven
by high Z sources then yes C coupled pickup could be a problem.

https://toshiba.semicon-storage.com/content/dam/toshiba-ss-v3/master/en/semiconductor/knowledge/e-learning/cmos-logic-usage-considerations/cmos-logic-uc-e.pdf

Note circuit incomplete, it needs a series R bewteen RC junction and gate input, in case
supply collapse on turn off rapidly dischrging cap thru input protection circuitry in CMOS
logic can cause damage.

 

[jonas123]

Hi everyone,
I’m using a JK flip-flop for a simple state control circuit. Pressing the push button should toggle once, but sometimes the output changes twice or returns to the previous state.

The button has only a resistor and capacitor debounce network.

Questions:

1. Is the issue likely incomplete debouncing or clock edge sensitivity?
2. Would a Schmitt trigger between the button and clock input solve it properly?
3. On the PCB, should manual input traces be protected from nearby switching lines?

What you describe sounds more like incomplete debouncing than JK clock sensitivity. A JK FF will happily react to every threshold crossing, so a bouncing button can look like multiple clock edges and cause double toggles.


An RC alone is often not enough because the clock input may linger in the undefined region. Adding a Schmitt trigger after the RC is usually the cleaner fix.


For PCB layout: yes, keep manual input traces away from fast switching nodes, clocks, gate drive traces, and high dI/dt paths. Add a solid ground reference and keep the button line short if possible.