All ceramic bypass cap design

[Spehro Pefhany]

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Best regards,
Spehro Pefhany

 

[John Woodgate]

I read in sci.electronics.design that Spehro Pefhany <speffSNIP@interlog

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Track inductance MUST be taken into account, so what you are asking is
whether a potentially multi-resonant circuit with localized damping is a
good idea.

The answer has to be a definite 'maybe'.

 

[John Larkin]

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Best regards,
Spehro Pefhany

For a multilayer, I like to fab the board with a very thin dielectric
layer between the Vcc and ground planes, and scatter a modest number
of maybe 0.1 uF surfmount ceramics around the board. This seems to
work very well, verified by some TDR experiments. I think that the
popular habit of Spice modeling equivalent bypass cap circuits is
silly, because the pcb planes are a huge, very low impedance, fairly
lossy transmission line. I know a guy who doesn't use bypass caps at
all, and his stuff works.

Of course, if you expect low-frequency current steps, you'll need
additional microfarads of energy storage.

John

 

[Spehro Pefhany]

For a multilayer, I like to fab the board with a very thin dielectric
layer between the Vcc and ground planes, and scatter a modest number
of maybe 0.1 uF surfmount ceramics around the board. This seems to
work very well, verified by some TDR experiments. I think that the
popular habit of Spice modeling equivalent bypass cap circuits is
silly, because the pcb planes are a huge, very low impedance, fairly
lossy transmission line.

That would be nice, but I'm constrained to use 2-layer with copper
pour or 4-layer on the PCBs. There must be a huge difference in trace
inductance between those two options.

I know a guy who doesn't use bypass caps at all, and his stuff works.

Yeah. I've seen that. 8-( It doesn't always work *reliably* once it
gets off the bench, which can be costly for those who do such things
and rewarding (financially, if not intellectually) for those who fix
it for them.

Of course, if you expect low-frequency current steps, you'll need
additional microfarads of energy storage.

Nothing is over 40-50MHz digital and currents are limited to a couple
of hundred mA, and analog is more like mV than uV, so it's not very
unusual, but it has to pass FCC with a plastic housing. I think
4-layer is looking good.

Best regards,
Spehro Pefhany

 

[Joerg]

Spehro, someone on this forum came up with the 1:30 rule which I think is a good
one. He said that when looking at the resonant behavior of the caps one should
look for the widest "flat band" of suppression with the minimum number of cap
sizes. Makes sense to me although I must say I usually went for a lower ratio
between 1:10 and 1:20.

I'd just be careful with the really large ceramics and their exotic materials
which have gone unobtanium at times in the past. I have really gotten zinged by
Z5U once. Some factory in Asia went kaputt and we sat there high and dry, unable
to get any caps at all.

Regards, Joerg.

 

[Spehro Pefhany]

Spehro, someone on this forum came up with the 1:30 rule which I think is a good
one. He said that when looking at the resonant behavior of the caps one should
look for the widest "flat band" of suppression with the minimum number of cap
sizes. Makes sense to me although I must say I usually went for a lower ratio
between 1:10 and 1:20.

Okay, the main concern with possible ringing on the supply lines due
to the inductance and "too good" ceramic caps vs. the usual high-ESR
tantalums or aluminum electrolytics. I don't really think bypassing
will be an issue here.

I'd just be careful with the really large ceramics and their exotic materials
which have gone unobtanium at times in the past. I have really gotten zinged by
Z5U once. Some factory in Asia went kaputt and we sat there high and dry, unable
to get any caps at all.

Regards, Joerg.

I'm stuck with X7R parts anyway (and therefore relatively big ones-
too big for the cell phone guys to hoard) because of the wide
temperature range.

Best regards,
Spehro Pefhany

 

[Joerg]

Spehro, bypassing may be a little bit of an issue here. In your case of a plastic
enclosure it may be needed to avoid too much in switching transients to show up on
the power plane/traces and then on the EMC analyzer. Don't know what logic you'll use
but even modest CMOS produces stuff above 30MHz. However, this can be handled by
pretty small caps.

Regards, Joerg.

 

[Tam/WB2TT]

With SM, you can get by with larger ceramic caps before they go high
impedance on you. On a 60 MHz digital/analog board, I found a few added .33
uf parts did the best job. I had the digital and analog VCC separated with a
~5uh RFC.

Tam

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Best regards,
Spehro Pefhany

http://www.speff.com

 

[John Larkin]

That would be nice, but I'm constrained to use 2-layer with copper
pour or 4-layer on the PCBs. There must be a huge difference in trace
inductance between those two options.


Yeah. I've seen that. 8-( It doesn't always work *reliably* once it
gets off the bench, which can be costly for those who do such things
and rewarding (financially, if not intellectually) for those who fix
it for them.


Nothing is over 40-50MHz digital and currents are limited to a couple
of hundred mA, and analog is more like mV than uV, so it's not very
unusual, but it has to pass FCC with a plastic housing. I think
4-layer is looking good.

Best regards,
Spehro Pefhany

I'd guess that 50 MHz logic, double-sided, plastic case would be
dicey. You could maybe make it work, but you might need to test 5
times to get it to pass.

I have a pretty good book about that very issue... hmmm, can't find
the damned thing, gotta look some more.

John

 

[Spehro Pefhany]

I'd guess that 50 MHz logic, double-sided, plastic case would be
dicey. You could maybe make it work, but you might need to test 5
times to get it to pass.

I have a pretty good book about that very issue... hmmm, can't find
the damned thing, gotta look some more.
John

_Noise Reduction Techniques in Electronic Systems_ ?

Best regards,
Spehro Pefhany

 

[John Larkin]

_Noise Reduction Techniques in Electronic Systems_ ?

Best regards,
Spehro Pefhany

No, I think it's this one:

http://www.amazon.com/exec/obidos/t..._books_3/002-5612395-0338429?v=glance&s=books

It's around here somewhere...

I talked to the author one day... he has a consulting company, too.
After some conversation, I mentioned my product would be in a metal
box, and he snorted... no challenge, apparently.

John

 

[Jan Panteltje]

For a multilayer, I like to fab the board with a very thin dielectric
layer between the Vcc and ground planes, and scatter a modest number
of maybe 0.1 uF surfmount ceramics around the board. This seems to
work very well, verified by some TDR experiments. I think that the
popular habit of Spice modeling equivalent bypass cap circuits is
silly, because the pcb planes are a huge, very low impedance, fairly
lossy transmission line. I know a guy who doesn't use bypass caps at
all, and his stuff works.

Funny you mention that, I had a board with 30 TTL chips and one 100 nF
poly cap.... And worked very well.
Sort of thought it was due to the chips own capacity.
It was not because of trace capacitance, because it was wire wrap...
JP

 

[Roy McCammon]

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Just my opinion, but some intentional esr can be a good thing.

I think of this way, the two planes are very close together
vs their width, so you can think of the two planes as a big
wide parallel plate transmission line with an impedance of
Z = (477 /sqrt(e))* t/w where w is the width and t is the
separation. Because I'm a contrarist, lets work with the
characteristic admittance, instead of impedance.

Y = w * sqrt(e) / (477*t)

Lets take t = .005 inches and e = 4. The formula becomes

Y = w * /1.2

which can be interpreted as saying every inch of w adds
the admittance of a 1.2 ohm resister.

Lets say that you are interested in frequencies up to 1GHz. The
velocity of light for e = 4 is about 6 inch/ns so one wavelength is
6 inches. And lets say that any separation less than one wavelength/6
(or one inch) is insignificant.

So, we could do a pretty good job of killing ringing by
putting a (capacitivly coupled) 1.2 ohm resister every inch
along the edge.

But maybe 1 wavelength over 6 is over kill. Maybe you are
comfortable with wave length/4. Then you can put a
0.8 ohm resister every 1.5 inches. And maybe you have some low
dielectric constant circuit board with sqrt(e) = 1.5 then you
get to space your resisters 4/3 farther apart.

I always figure a few lousy esr electrolytics can be considered
as capacitivly coupled low value resisters, so putting them every
so often around the board edge is also a good idea.

But that's just me rambling.

 

[Roy McCammon]

Funny you mention that, I had a board with 30 TTL chips and one 100 nF
poly cap.... And worked very well.
Sort of thought it was due to the chips own capacity.
It was not because of trace capacitance, because it was wire wrap...
JP

well, I guess I've never had a design that didn't work and was fixed by
adding more individual bypass caps.

 

[John Larkin]

well, I guess I've never had a design that didn't work and was fixed by
adding more individual bypass caps.

Or, to put it another way, I've never designed a board that had too
few bypasses.

John

 

[Greg Neff]

From a bypass and EMC viewpoint would it be a good idea to use a
relatively large ceramic cap with a series R of perhaps 1 ohm in
parallel with distributed smaller capacitors across the individual
chips?

Best regards,
Spehro Pefhany

On our boards we use only ceramic capacitors for decoupling. This
includes X5R and X7R up to 10uF, in addition to 0.1uF devices
(sometimes multiple) per IC.

I look at the power source to decide about adding resistance. If the
regulator supplying the power requires some output ESR for stability,
then I add some resistance in series with the big caps. For example,
if a regulator requires an ESR range of 0.1 to 1 ohms for stability,
then I might provide four or five 1 ohm + 10uF RC sets on the board.
If the regulator can tolerate the low ESR of ceramics, then I omit the
resistors.

This strategy has worked well for us on many designs, with thousands
of boards in the field. We use fast CPLDs, FPGAs, and bus speeds of
up to 50MHz (up to 72 bits wide). All our boards use power and ground
planes.

So far, we have been able to get away with this rule of thumb. As the
logic speeds increase we will have to be more analytical about
decoupling. I'm not looking forward to that day.

I'm not sure how adding resistors would affect EMC. It's probably PCB
and system dependant. My primary concern is making sure that I don't
destabilise the power source.


================================

Greg Neff
VP Engineering
*Microsym* Computers Inc.
[email protected]

 

[John Woodgate]

I read in sci.electronics.design that Greg Neff <[email protected]>

I'm not sure how adding resistors would affect EMC. It's probably PCB
and system dependant. My primary concern is making sure that I don't
destabilise the power source.

Well, if the power source oscillated that would be one BIG EMC issue. So
your technique is a step in the right direction. Just don't use any more
resistance that necessary, and THEN check that any track
inductance/decoupling cap resonances that might be excited by trash from
the chips are low-Q.

 

[Ian Buckner]

I read in sci.electronics.design that Greg Neff <[email protected]>


Well, if the power source oscillated that would be one BIG EMC issue. So
your technique is a step in the right direction. Just don't use any more
resistance that necessary, and THEN check that any track
inductance/decoupling cap resonances that might be excited by trash from
the chips are low-Q.

This week's EDN Design Ideas section has a suggestion to use an
X-form capacitor for decoupling, claims a single one will replace
the usual bunch of different values, and avoids the parallel
resonances
between the series resonant notches. No opinion, I've not tried it,
just for information.

Regards
Ian

 

[SioL]

This week's EDN Design Ideas section has a suggestion to use an
X-form capacitor for decoupling, claims a single one will replace
the usual bunch of different values, and avoids the parallel
resonances
between the series resonant notches. No opinion, I've not tried it,
just for information.

Regards
Ian

What is an X-form capacitor?

PCS

 

[Joerg]

Just checked EDN Design Ideas and couldn't find X-form. Do you have a
link?

Regards, Joerg.