D flip flop datasheet

[vead]

I have googled and saw datasheet for D flip flop like D flip flop with set and reset positive edge i think it is complete Ic for d flip flop circuit

now I have googled and saw datasheet for d flip flop verilog code
that was
1) D flip flop set with positive edge
2) D flip flop rest with positive edge
3) D flip flop with set rest positive edge

my question is that why d flip flop make different type in verilog while d flip flop make single like D flip flop with set rest positive edge in digital logic

 

[(*steve*)]

To fully specify the flip-flop you need to know things like the edge that edge sensitive inputs are sensitive to.

If this is not specified in the verilog code then you'll need to investigate it because each different combination can cause it operate significantly differently in an actual application.

 

[vead]

To fully specify the flip-flop you need to know things like the edge that edge sensitive inputs are sensitive to.

If this is not specified in the verilog code then you'll need to investigate it because each different combination can cause it operate significantly differently in an actual application.

I made hardware with veriolog code for below

1) D flip flop set with positive edge
2) D flip flop rest with positive edge

does it work as hardware

 

[Harald Kapp]

does it work as hardware

How are we to know? You haven't even shown your code.
If the code works in the verilog testbench (simulator), then it should work in hardware, too.

 

[(*steve*)]

Also note that the edge sensitivity of the clock has not been specified.

 

[vead]

ok , simple D flip flop means one clock input data input Q and Q0 then we can set and reset the flip flop now this is complete Ic for d flip flop now we can say " D flip flop with set rest
in verilog we can write code for D flip flop with set reset

my question is that why we write code for D flip flop with set or D flip flop with reset while we can write code for D flip flop with set reset

 

[(*steve*)]

Perhaps if you have to squeeze in as much as you can into limited resources you would not implement features you don't need.

If you don't need the reset input then why code for it?

 

[Harald Kapp]

my question is that why we write code for D flip flop with set or D flip flop with reset while we can write code for D flip flop with set reset

A FlipFlop with set and reset is rather universal. You can always tie the unused input to a fixed potential. A good Verilog compiler will recognize that the input is never used and minimize the logic to eliminate the unused gates.