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petrus bitbyter
- Jan 1, 1970
- 0
matt said:Really? Ugh - confusing!
Same board, yup (well, same design, same manufacturer, etc).
Same GAL type: GAL16V8D - not sure what speed or brand he used though
as he's not replying to his emails.
I'll quote from the chap who came up with the JEDEC:
"All ROM and RAM on this Memory Board is initially decoded by the
82s153 FPLA at location U10. The FPLA enables address decoders based
on the upper 3 address bits of the address bus. Additionally, the FPLA
prevents ROM and RAM access during certain system processes including:
refresh cycles, active resets, I/O requests and a architecture
specific signal called /BUZOFF. The FPLA contains 5 address inputs and
7 status line inputs. Outputs of the FPLA are 4 decoder enable lines
and 1 transceiver direction select line. The enable line for ROMs X1
through X4 (74LS139 at U8, pin 1) is selected on addresses x0000-x3fff
( !a15, !a14). The 4 ROMs are then selected off of a13 and a 12 by the
lower half of the 139 decoder at U8. All the other selects work
similarly. The second half of U8 (pin 15, enable) selects ROMs X5-X8
(a15, !a14), the lower half of U9 (pin 1, enable) selects the ROMs at
X9 and X10 (a15, a14, !a13)and the upper half of U9 (pin 15 enable)
selects one of the 4 RAMs (a15, a14, a13) based on address lines a11
and a12).
The FPLA also selects the direction of the 74ls245 transceiver at U17.
On a write, pin 1 of U17 is held high to allow data to flow from the
processor data bus to the RAM/ROM board data bus, on a read the line
is held low and the data flows in the opposite direction. Most of the
additional circuitry on the ROM board deals with selecting the RAM at
X21 for high score and setup information. The three 74ls244s at U16,
U15 and U 11 are all used as line drivers with all of their select
lines tied low permanently.
The original FPLA used is a Signetics 82s153, which is now obsolete, a
modern replacement is a Signetics pls153, however I have not been able
to get a good copy of one so I had to write a replacement using a PLD
(GAL16V8D)."
Here it is from the guy's site:
http://web.archive.org/web/20020331203553/http://my.erinet.com/~jamesm/tech/roto/roto.jed
I don't know how to extract a page or two from a PDF, but the whole
manual (12 MBytes! with schems at the end) can be found in this file:
http://arcarc.xmission.com/PDF Arcade Manuals and Schematics/Robby Roto.pdf
you'll need to look at the for the 'Memory Board'. The device in
question is the PLS at location U10
BTW, the quality of the schems is poor in places, but just about
readable.
Many thanks.![]()
I'm really puzzled. Had a look at the schematics. The device is supposed to
do straight forward address decoding. No latches, no tricks no reason to
think the GAL to be too fast. Had a look at the JEDEC as well. Did not check
it out up to the last bit but as far as I can see it is programmed to do
what the GAL guy said. What's more, a correctly programmed GAL should be
pin-compatible with the original 82S153. There's only one nasty possibillity
I can think about: there have been GALs on the market that did not meet the
full specs due to a mask fault. The company made new masks and sold the old
ones to another firm that used them to made there own GALs, including the
flaw. I never had a problem myself so it's only hearsay. Besides I'm not
sure the D-types were effected, but you may have run into this old problem.
You can make some hardware to compare the 82S153 and the GAL16V8D. An EPP
printerport, some LS364 latches and a LS245 buffer on a breadboard is all
you need. Feed the DUT with a counter, read back all outputs and save the
results on disk. Read the next device and compare the results.
Can't you find someone with a programmer that can read the old 82S153? It's
only combinatotial logic and FAIK they had no security bit. Somewhere I
still should have the software to make equationfiles from the JEDEC. It's
easier then building hardware.
petrus bitbyter