[John Larkin]

Red is less visible than blue on the circuit card assembly.

Not against blue solder mask, which ours is.


Neither is

glaringly obvious to anyone examining a board unless he is specifically
looking for such things.

Also, not all are kludges. Some get approvals, and all future boards
have to be built that way, or it simply does not qualify to be called
that particular assembly.

We never ship anything that's not authorized by an ECO. But a kluge is
always a kluge.

John

 

[Joerg]

...or the schematic capture/layout software can produce PDFs, as at least
Viewlogic and Pulsonix can: Everyone already knows how to "click around"
through PDFs (e.g., clicking on a hierarchical block pushes down into the
hierarchy) and use the "Search" command.

.... and then Adobe Reader crashes. Again.

 

[Archimedes' Lever]

We had a more brutal method of shame at my first job: Every jumper
resulted in a scratch mark behind your name on a bulletin board in the
tech area. Plus 5c into the beer kitty. When $10 had accumulated another
crate of brewsky was purchased.

Sounds more like an incentive. D'oh!

 

[krw]

I can add one that crashes more, on all computers here: Adobe Acrobat
Reader. But I guess everyone knows that.

[...]

Mine is all updated, and has NEVER crashed.

When you attempt to print a large pdf, you should locally spool the
print job first. If you do not know how to set your printer/computer up
to spool properly, you deserve to have crashes until someone guides you
through the process.

Operator error... again.

Adobe is bloatware spyware crap. Even if it didn't crash, it's
amazingly slow. Get Foxit Reader and CutePDF and see the difference.

I have a lot of stuff that CutePDF won't print. I've found that
PDFCreator is much better. I too use Foxit, but it is ugly.

 

[krw]

krw wrote:
John Larkin wrote:
John Larkin wrote:
John Larkin wrote:
[...]

I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff
What happens to reference designators in a hierarchical schematic?

Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.

I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Yes, it just starts with the next available number at block 1, then goes
on to block 2 and so on until all sub-sheets are done. For proper
documentation you must let it print out all 16 blocks, otherwise a
technician could never repair the unit. For a design review you don't
necessarily have to (in med or aero and such you usually do).
We're planning on setting the service and test departments up with
schematic viewers so they can use the hierarchy.

Hey, did you start modernizing the place? When I did that the first time
it was met with quite a bit of resistance. Until they started feeling
the benefits. "How did you get that stock room quantity?" ... "From my
computation machine." ... "Oh."

If I have anything to do with it... They already have the PCs, but
use them to view PDFs.

I think I finally got them to understand that engineering really needs
prices. Sometime in the future they're going to dump the purchasing
database into the parts database once a month. It's a start.
Quantity?

Quantity on hand should be in there as well. So that a rookie doesn't
design in the uA741 that purchasing still has to occasionally buy for
the old design that uncle Leroy did in the 70's.

I'll be happy with the price. There are only two of us doing any
hardware design and I know *I* won't be using a '741. ;-)

[...]

Next issue: how do you deal with multiple SKUs built off the same
schematics? They want us to manually edit the schematics for service.
I'm trying to convince them that they really don't want to do that. I
certainly don't want to be held responsible for multiple versions of
the same data.

Old rule: When only one part on the circuit board is changed in value it
is another assembly and must get another assy number. No ifs, buts or whens.

Sure, that's obvious but it still doesn't solve the schematic problem.
They want schematics for service to use[*]. We're experimenting with
"graying" (yellow, actually) out sections not implemented but it's
manual and quite labor intensive. The other problem we ran into was
that to select any component under the "fill" it has to be removed.
The fill will be selected first.

[*] I'm fighting this one.

 

[krw]

This is how Pulsonix does it as well, although I have used CAD packages that
would generate U1.1, U1.2, U1.3, etc. for each instance of a hierarchical
block, which does make things a little nicer, at least if you don't mind your
silkscreen also saying U1.!, U1.2, etc. The problem with this is that you're
then usually forced to use that package's layout tool as well, since AFAIK
there isn't a widely used PCB netlist format that really supports hierarchy.

As long as the layout tool doesn't barf on the '.' why would care
about the reference designator? It's just used for humans.

I have heard of a few enterprising individuals who wrote netlist translation
tools so that U1.1 would get turned into, e.g., U101, U1.2 becomes U102, etc.,
though -- and I've known people who did something similar manually for small
designs.

What about more than 100 components? We already have numbers as high
as 12xx, since we use the first two characters to signify schematic
page (and some pages already have more than 100 resistors and
capacitors, so get two).

I am all for printing everything out at some point, but these days your tech
is going to be sitting in front of a computer anyway, so sometimes it's faster
if they just pull up the schematic electronically and search for, e.g., R265
and some techs prefer this -- particularly field service guys -- since they're
not having to carry all those dead trees around.

I prefer paper for reference. The tube often is used for searching
the layout though.

 

[krw]

Usually I can't do that because the layouters all use other systems than
I do. When you must backannotate it's all over anyhow, it'll start with
U1 in the upper left of the board and so on.



Last year I taught a tech who was populating a prototype the use of a
Gerber viewer. That sure made life a lot easier for her.

At that point back-annotating loses it's importance. We don't back
annotate reference designators; not sure why.

 

[krw]

On Fri, 07 Aug 2009 18:13:37 -0700, John Larkin


On Fri, 07 Aug 2009 15:52:56 -0700, John Larkin

John Larkin wrote:
John Larkin wrote:
krw wrote:
krw wrote:
[...]


b. I often have situations where, say, an opamp or comparator switches
the supply of another. This can become next to impossible to understand
by other engineers, especially younger ones.
In our case there is always a PIC in the middle. I don't know how to
show the power control code on the schematic. ;-)

So far I never had a PIC in the middle ...
When I first wrote "PIC" I was kidding; the answer to every question
is "PIC". The fact is that we do have a PIC in the middle, on top of
a DSP.

Dead-bugged on top of it with liquid nails glue ...?


Cadsoft Eagle allows a very nice flexibility here: You can call up the
power pins via the "invoke" command. The CAD symbol is usually drawn so
it slides over the A-device (or another if you wish) and fits as if it
was part of the symbol. You can also place it near the group in the
schematic, or down at the bottom for simpler architectures. That's how
it ought to be, gives the designer all the freedom.
That sounds like it solves all the problems.
Sure does. That CAD program is very close to perfect. With one major
deficiency and that makes it IMHO useless for any larger design: No
hierarchical sheet structure :-(
Monday we had the design review for the widget I'm working on. My
boss really liked the hierarchical (turtles all the way down)
organization. I'm not so sure about the other hardware engineer
though. ;-) I'm still not to where I can easily determine where to
add a hierarchical block or another sheet though. More than one block
for a component (FPGA) just seems wrong.
Yes, I would never, ever, split a component across several sheets or
even just blocks. That makes a royal mess out of a schematic.
Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie,
backside bus, power) across two sheets. The FPGA is 8 sections (one
for each bank, 450 pins or so total) across three sheets. This one
board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

Nope. Only exception is simple logic gates but even then you'd almost
have to twist my arm.


I never do hierarchical schematics. Everything's flat.

Then we have almost opposite CAD habits. But at least we have similar
beer taste, only the good stuff

What happens to reference designators in a hierarchical schematic?


Typically it numbers right on through if you hit auto-number. But it
really never mattered to me in my Orcad days because most clients wanted
a back annotation anyhow, so that the top left of the physical PCB
started with R1, C1 and the bottom right would end with R542, C367. Then
that got fed into the schematic, I updated my module spec with the new
refdeses, done.


I don't understand that. If the schematic has a main controller part
and, say, 16 channels, and you draw one instance of the channel,
abstract that into a block, and draw 16 of the blocks - which is what
a hierarchical schematic does - how does each instance have its own
reference designators, sequantial across all the modules?

Capture renumbers - flat - them for each instance.

How do you print the schematic for field service? Where the hell is
R325 in one of the instances when only one sub-module schematic
exists?

They all exist. You print all the sheets. Ugly as hell, but it's
really not much worse than flat schematics. Much better if you use a
viewer.

Then the hierarchical thing doesn't seem to be much different than
just doing it flat.

If the most important thing in life is the cost of printer paper, you
may have a point. OTOH, hierarchies are easier to understand,
simulate, and reuse; sorta the point of schematics.

Somehow I don't have trouble understanding 16 sheets that are labeled
CHANNEL 0 through CHANNEL 15, each with all the reference designators
and connector pins in plain view.

And nothing would change if those sixteen sheets were instances of a
hierarchical block, except you'd have another higher level block that
would show their interconnect. IOW, more information.

IOW I'd have to chase all over various sheets to see which connector
pin is ultimately connected to U12 pin 5.

Progress?

Yes.

 

[krw]

Hmm... we should do that with software guys... pretty much free beer for
life...

Yeah, but they often get to fix theirs without it becoming public.
They get to decide what's released and with what caveats.

 

[krw]

If you hold down the tab key while you click, Capture will cycle through
overlapping objects?

Not sure, but I'll try it. I've had this trouble before with notes.

What would you prefer your services guys to use, out of curiosity? (Since you
said you were fighting the effort for them to have schematics like this?)

They have all the documentation and there are already assembly
drawings for every SKU. Some features just aren't on some units. The
schematic represents the "max" implementation, though that never gets
built (conflicting components).

 

[FatBytestard]

We never ship anything that's not authorized by an ECO. But a kluge is
always a kluge.

John

Not once it has been accepted for a product. Then, it becomes set in
stone. We have an 18 x 14 main board that has 4 FPGAs on it. There were
some terminations left out (actually, only the traces), so we hand wired
1/4" jumps to each of the needed pins. It really is not worth spinning
the board again.

This is done in all circles, including NASA gear, where providing an
additional production run of PCBs is more expensive than working with
what one has, depending, of course, on the complexity of the fix(es).

 

[Archimedes' Lever]

... and then Adobe Reader crashes. Again.

Only when there is an idiot at the helm.

 

[Fred Abse]

A pdf is a full bit map. Every pixel is defined and stored.

Not so. If the original artwork was vector graphics, it's in the .pdf as
vector. Witness the ease with which pdftoedit will pull .dxf out of .pdfs
containing original vector material.

Example: Jim Thompson's .pdf drawings ;-)

Makes sense, too. Much smaller files.

 

[Jim Thompson]

Not so. If the original artwork was vector graphics, it's in the .pdf as
vector. Witness the ease with which pdftoedit will pull .dxf out of .pdfs
containing original vector material.

Example: Jim Thompson's .pdf drawings ;-)

Makes sense, too. Much smaller files.

Yep. Marginally smaller file size than PNG, significantly smaller
than GIF or JPG, MUCH better readability.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine Sometimes I even put it in the food

 

[Fred Abse]

Witness the ease with which pdftoedit will pull .dxf out of .pdfs
containing original vector material.

s/pdftoedit/pstoedit

 

[Fred Abse]

Yep. Marginally smaller file size than PNG, significantly smaller
than GIF or JPG, MUCH better readability.

Theoretically infinite scalability - just math.

 

[Jim Thompson]

Theoretically infinite scalability - just math.

Only as long as the source material is all vector.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine Sometimes I even put it in the food

 

[Fred Abse]

Only as long as the source material is all vector.

True.

 

[Archimedes' Lever]

Theoretically infinite scalability - just math.

The print jobs are bit mapped graphics, just like I said. That is how
it is compiled, and sent to the printer.

 

[Rich Grise]

I court that would be one count of inattentiveness and 15 counts of
negligence. And John agreed that he'd be willing to bring punishment
onto himself should that ever happen ;-)

We use red kluge wires, like the Scarlet Letter, to make the shame
more public.
[/QUOTE]
Uh, this is humour, right? ;-)

Cheers!
Rich