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In static situation the power dissipation is very low, depending if the CMOS is "full-digital" or in some degree analog. With analog some current is needed to maintain the analog-voltages inside the chip. With digital this current is very minimal.

When CMOS is switching state, the device consumes more current.

This is because the FET-transistors inside the CMOS is changing state, thus requiring that the gate-capasitance to be carged/discharged. This is the main point where the energy is needed.

Dissipation is a measure of the energy required to charge/discharge these capasitances through internal resisrance.

The faster the transition speed, the more current is needed, but less time.

The bigger the capasitance, the more energy is needed and more time.

The smalle the internal resistance, the more current is needed. (but shorter time)

With some older CMOS devices there was some design-"faults", which ment that in some transitions two transistors were conducting at the same time very very briefly and made a short-circuit for this brief moment. But in modern devices this is not happening.

Hope this helps..?

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