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postive edge triggered D flipflop

Guest bhuvaneshnick

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Guest bhuvaneshnick

In the above circuit if clock(CLK 1) goes from 0 to 1 and input D =0 ,this makes Q=0.
It is stated that when the clock is at HIGH(1) any further change in input does not affect output,how it is so .Can you explain me  please.Thank you in advance


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  • 1 year later...

Same confusion landed me here, but I wondered no answer till now. However I figured out the answer.

@bhuvaneshnick I want to correct you that in D type Flip-Flop when Clock pulse is Low (not high) then there is no change in output. Look at the below Diagram, its clear if clock Pulse is low then the the output of first two NAND gates (A and B ) are 1, and output Q (and Q') doesn't changes its state as one of the input for NAND gates X and Y is 1. Means if the output Q is 1 then it remains 1 and if 0 then it remains 0.


Check this Clap switch and find "Working of D-type Flip-flop" , It is in very simple language from where I got it. Also I strongly recommend you to learn about S-R Flip flop before D-type flip flop.

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