Jump to content
Electronics-Lab.com Community

Parallel MAC unit based on modified booth algorithm [Help needed]

Guest gstekboy

Recommended Posts

Guest gstekboy

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time.

The partial product summation + accumulation unit of above parallel mac is given below. (link to the image).


My problem : When I give input to multiplier as 00000101(5) and 00001000( 8 ) what will be the values produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3 that can be used as input of partial product generation + accumulation stage.

The complete document is shared below.

Please share your ideas.I need to continue my project based on your replies.


Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...